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參數(shù)資料
| 型號： | CS51024ED16 |
| 廠商： | ZF Electronics Corporation |
| 英文描述： | Enhanced Current Mode PWM Controller |
| 中文描述： | 增強(qiáng)電流模式PWM控制器 |
| 文件頁數(shù)： | 7/9頁 |
| 文件大?。?/td> | 170K |
| 代理商： | CS51024ED16 |
7
input of the PWM comparator is a combination of these
two voltages. The slope compensation,
lated using the following formula:
, is calcu-
= 0.1
×
It should be noted that internal capacitance of the IC will
cause an error when determining slope compensation
capacitance C
S
. This error is typically small for large val-
ues of C
S
, but increases as C
S
becomes small and compara-
ble to the internal capacitance. The effect is apparent as a
reduction in charging current due to the need to charge
the internal capacitance in parallel with C
S
. Figure 3 shows
a typical curve indicating this decrease in available charg-
ing current.
Figure 3: The slope compensation pin charge current reduces when a
small capacitor is used.
Undervoltage (UV) and Overvoltage (OV) Monitor
Two independent comparators monitor OV and UV con-
ditions. A string of three resistors is connected in series
between the monitored voltage (usually the input voltage)
and ground (see Figure 4). When voltage at the OV pin
exceeds 2.5V, an overvoltage condition is detected and
GATE shuts down. An internal 12.5μA current source
turns on and feeds current into the external resistor, R
3
,
creating a hysteresis determined by the value of this resis-
tor (the higher the value, the greater the hysteresis). The
hysteresis voltage of the OV monitor is determined by the
following formula:
V
OV(HYST)
= 12.5μA
×
R
3
where R
3
is a resistor connected from the OV pin to ground.
When the monitored voltage is low and the UV pin is less
than 1.45V, GATE shuts down. The UV pin has fixed 75mV
hysteresis.
Both OV and UV conditions are latched until the Soft Start
capacitor is discharged. This way, every time a fault con-
dition is detected the controller goes through the power
up sequence.
Figure 4: UV/OV Monitor Divider
To calculate the OV/UV resistor divider:
1. Solve for R
3
, based on OV hysteresis requirements.
V
OV(HYST)
×
2.5V
V
MAX
×
12.5μA
R
3
=
’
where V
OV(HYST)
is the desired amount of overvoltage hys-
teresis, and V
MAX
is the input voltage at which the supply
will shut down.
2. Find the total impedance of the divider.
R
TOT
= R
1
+ R
2
+ R
3
=
3. Determine the value of R
2
from the UV threshold condi-
tions.
1.45
×
R
TOT
V
MIN
R
2
=
R
3,
where V
MIN
is the UV voltage at which the supply will
shut down.
4. Calculate R
1
.
R
1
= R
TOT
R
2
R
3
5. The undervoltage hysteresis is given by:
V
UV(HYST)
=
Synchronization
A bi-directional synchronization is provided to synchro-
nize several controllers. When SYNC pins are connected
together, the converters will lock to the highest switching
frequency. The fastest controller becomes the master, pro-
ducing a 4.3V, 200ns pulse train. Only one, the highest fre-
quency SYNC signal, will appear on the SYNC line.
Sleep
The sleep input is an active high input. The CS51022/51024
is placed in sleep mode when SLEEP is driven high. In
sleep mode, the controller and MOSFET are turned off.
Connect to Gnd for normal operation. The sleep mode
operates at V
CC
≤
15V.
Oscillator and Duty Cycle Limit
The switching frequency is set by R
T
and C
T
connected to
the R
T
C
T
pin. C
T
charges and discharges between 3V and
1.5V.
The maximum duty cycle is set by the ratio of the on time,
t
ON
, and the whole period,
T = t
ON
+ t
OFF
. Because the
V
MIN
×
0.075
1.45
V
MAX
×
R
3
2.5
V
IN
V
UV
V
OV
R
3
R
2
R
1
60
55
50
45
40
35
30
25
20
10
100
1000
C
μ
A
Compensation Cap (pF)
53μA
C
S
dV
SLOPE
dt
dV
SLOPE
dt
Circuit Description: continued
C
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