參數(shù)資料
型號: CS51024EDR16
廠商: ZF Electronics Corporation
英文描述: Enhanced Current Mode PWM Controller
中文描述: 增強電流模式PWM控制器
文件頁數(shù): 5/9頁
文件大?。?/td> 170K
代理商: CS51024EDR16
C
5
Package Pin Description: continued
PACKAGE PIN #
PIN SYMBOL
FUNCTION
+
-
4.75V
V
REF
DISABLE
55ns
1.33
55
μ
A
VREF = 5V
OSC
Discharge
Latch
2.5V
PWM
S
R
Q
+
E/A
+
START
STOP
+
-
SET
I
SS
Clamp
12.5
μ
A
OV
MonUV
+
0.1V
0.1
+
V
REF
53
μ
A
2V
V
REF
_OK
Vcc_OK
MonSS
V
Monitor
+
1.45V
×
0.8
10k
20k
V
REF
13.5V
V
ISense
2.5V
4.3V
200ns
G1
F1
G2
D1
Q2
G3
FAULT
ZD1
D4
+
4.7V
D2
D3
SS
PGnd
V
C
GATE
I
SENSE
SLOPE
COMP
V
FB
OV
I
SET
V
REF
V
CC
LGnd
SYNC
R
T
C
T
UV
×
G4
×
SLEEP
2nd
Figure 1: CS51021/22/23/24 Block Diagram
Block Diagram
16L PDIP & SO Narrow
7
R
T
C
T
Timing resistor R
T
and capacitor C
T
determine oscillator frequen-
cy and maximum duty cycle, D
MAX
.
8
I
SET
Voltage at this pin sets pulse-by-pulse overcurrent threshold, and
second threshold (1.33 times higher) with Soft Start retrigger (hic-
cup mode).
9
V
FB
Feedback voltage input. Connected to the error amplifier invert-
ing input.
10
COMP
Error amplifier output. Frequency compensation network is usu-
ally connected between COMP and V
FB
pins.
11
SS
Charging external capacitor restricts error amplifier output volt-
age during the start or fault conditions (hiccup).
12
LGnd
Logic ground.
13
V
REF
5.0V reference voltage output.
14
V
CC
Logic supply voltage.
15
PGnd
Output power stage ground connection.
16
V
C
Output power stage supply voltage.
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