參數(shù)資料
型號(hào)： CS5127GDW16
廠商： ZF Electronics Corporation
英文描述： Dual Output Nonsynchronous Buck Controller with Sync Function and Second Channel Enable
中文描述： 非同步雙輸出同步降壓控制器的功能及第二通道啟用
文件頁(yè)數(shù)： 14/24頁(yè)
文件大小： 293K
代理商： CS5127GDW16
14
Applications Information: continued
IC. This heat is transferred to the surface of the IC package,
but a thermal gradient exists due to the thermal properties
of the package molding compound. The magnitude of this
thermal gradient is denoted in manufacturers data sheets
as
Q
JA
, or junction-to-air thermal resistance. The on-chip
junction temperature can be calculated if
Q
JA
, the air tem-
perature at the ICs surface and the on-chip power
dissipation are known:
T
J
= T
A
+ (
Q
JA
′
P)
T
J
and T
A
are given in degrees centigrade, P is IC power
dissipation in watts and
Q
JA
is thermal resistance in
degrees centigrade per watt. Junction temperature should
be calculated for all semiconductor devices to ensure they
are operated below the manufacturers maximum junction
temperature specification. If any components temperature
exceeds the manufacturers maximum specification, some
form of heatsink will be required.
Heatsinking will improve the thermal performance of any
IC. Adding a heatsink will reduce the magnitude of
Q
JA
by
providing a larger surface area for heat transfer to the sur-
rounding air. Typical heat sinking techniques include the
use of commercial heatsinks for devices in TO-220 pack-
ages, or printed circuit board techniques such as thermal
bias and large copper foil areas for surface mount pack-
ages.
When choosing a heatsink, it is important to break
Q
JA
into several different components.
Q
JA
=
Q
JC
+
Q
CS
+
Q
SA
where all components of
Q
JA
are given in C/W.
Q
JC
is the thermal impedance from the junction to the sur-
face of the package case. This parameter is also included in
manufacturers data sheets. Its value is dependent on the
mold compound and lead frames used in assembly of the
semiconductor device in question.
Q
CS
is the thermal impedance from the surface of the case
to the heatsink. This component of the thermal impedance
can be modified by using thermal pads or thermal grease
between the case and the heat sink. These materials replace
the air gap normally found between heatsink and case with
a higher thermal conductivity path. Values of
Q
CS
are
found in catalogs published by manufacturers of heatsinks
and thermal compounds.
Finally,
Q
SA
is the thermal impedance from the heatsink to
ambient temperature.
Q
SA
is the important parameter
when choosing a heatsink. Smaller values of
Q
SA
allow
higher power dissipation without exceeding the maximum
junction temperature of the semiconductor device. Values
of
Q
SA
are typically provided in catalogs published by
heatsink manufacturers.
The basic equation for selecting a heatsink is
P
D
=
where P
D
is on-chip power dissipation in watts, T
J
is junc-
tion temperature in C, T
A
is ambient temperature inC,
and thermal impedance
Q
JC
,
Q
CS
, and
Q
SA
are inC/W.
All these quantities can be calculated or obtained from data
sheets. The choice of a heatsink is based on the value of
Q
SA
required such that the calculated power dissipation
does not cause junction temperature to exceed the manu-
facturers maximum specification.
Switching regulators generate noise a consequence of the
large values of current being switched on and off in normal
operation. Careful attention to layout of the printed circuit
board will usually minimize noise problems. Layout guide-
lines are provided in the next section. However, it may be
necessary in some cases to add filter inductors or bypass
capacitors to the circuitry to achieve the desired perfor-
mance.
The following guidelines should be observed in the layout
of PC boards for the CS5127:
1. Connect the PGND lead to the external ground with a
wide metal trace.
2. Connect both LGND and PGND together with a wide
trace as close to the IC as possible.
3. Make all ground connections to a common ground
plane with as few interruptions as possible. Breaks in
the ground plane metal should be made parallel to an
imaginary line between the supply connections and the
load.
4. Connect the ground side of the COMP lead capacitors
back to LGND with separate traces.
5. Place the V
FFB
lead capacitors as close to the V
FFB
leads
as possible.
6. Place the 5V line bypass capacitors as close to the
switch FETs as possible.
7. Place the output capacitor network as close to the load
as possible.
8. Route the GATE lead signals to the FET gates with a
metal trace at least 0.025 inches wide.
9. Use wide straight metal traces to connect between the
5V line and FETs, between FETs and inductors and
between inductors and loads to minimize resistance in
the high current paths. Avoid sharp turns, loops and
long lengths.
Layout Considerations
EMI Management
T
J
- T
A
Q
JC
+
Q
CS
+
Q
SA
C
相關(guān)PDF資料
PDF描述
CS5127GDWR16 Dual Output Nonsynchronous Buck Controller with Sync Function and Second Channel Enable
CS5127 Dual Output Nonsynchronous Buck Controller with Sync Function and Second Channel Enable
CS51311GDR14 Synchronous CPU Buck Controller for 12V and 5V Applications
CS51311 Synchronous CPU Buck Controller for 12V and 5V Applications
CS51311GD14 Synchronous CPU Buck Controller for 12V and 5V Applications
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CS5127GDWR16 制造商:Rochester Electronics LLC 功能描述:- Bulk
CS5128AF 制造商:Rochester Electronics LLC 功能描述:- Bulk
CS5-12IO2 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Netzthyristoren Phase control thyristors
CS51311GD14 制造商:Rochester Electronics LLC 功能描述:- Bulk
CS-51313D16 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Current-Mode SMPS Controller
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*