參數(shù)資料
型號(hào): CS51311
廠商: ZF Electronics Corporation
英文描述: Synchronous CPU Buck Controller for 12V and 5V Applications
中文描述: 同步降壓控制器的CPU為12V和5V的應(yīng)用
文件頁數(shù): 8/19頁
文件大?。?/td> 239K
代理商: CS51311
C
8
Application Information: continued
regulator output exceeds the voltage on the COMP pin
plus the 1.1V PWM comparator offset prior to the drop
across the current sense resistor exceeding the current limit
threshold. In this case, the PWM control loop has achieved
regulation and the initial pulse is then followed by a con-
stant off time as programmed by the C
OFF
capacitor. The
COMP capacitor will continue to slowly charge and the
regulator output voltage will follow it, less the 1.1V PWM
offset, until it achieves the voltage programmed by the
DAC’s VID input. The Error Amp will then source or sink
current to the COMP cap as required to maintain the cor-
rect regulator DC output voltage. Since the rate of increase
of the COMP pin voltage is typically set much slower than
the regulator’s slew capability, inrush current, output volt-
age, and duty cycle all gradually increase from zero. (See
Figures 7, 8, and 9).
Figure 7: Normal Startup (2ms/div).
Channel 1 - Regulator Output Voltage (1V/div)
Channel 2 - COMP Pin (1V/div)
Channel 3 - V
CC
(10V/div)
Channel 4 - Regulator Input Voltage (5V/div)
Figure 8: Normal Startup showing initial pulse followed by Soft Start
(20μs/div).
Channel 1 - Regulator Output Voltage (1V/div)
Channel 2 – Inductor Switching Node (5V/div)
Channel 3 - V
CC
(10V/div)
Channel 4 - Regulator Input Voltage (5V/div)
Figure 9: Pulse-by-Pulse Regulation during Soft Start (2μs/div).
Channel 1 - Regulator Output Voltage (1V/div)
Channel 2 – Inductor Switching Node (5V/div)
Channel 3 - V
CC
(10V/div)
Channel 4 - Regulator Input Voltage (5V/div)
If the voltage across the Current Sense resistor generates a
voltage difference between the V
FB
and V
OUT
pins that
exceeds the OVC Comparator Offset Voltage (86mV typi-
cal), the Fault latch is set. This causes the COMP pin to be
quickly discharged, turning off GATE(H) and the upper
NFET since the voltage on the COMP pin is now less than
the 1.1V PWM comparator offset. The Fault latch is reset
when the voltage on the COMP decreases below the
Discharge threshold voltage (0.25V typical). The COMP
capacitor will again begin to charge, and when it exceeds
the 1.1V PWM comparator offset, the regulator output will
Soft Start normally (see Figure 10).
Because the start-up circuit depends on the current sense
function, a current sense resistor should always be used.
Figure 10: Startup with COMP pre-charged to 2V (2ms/div).
Channel 1 - Regulator Output Voltage (1V/div)
Channel 2 - COMP Pin (1V/div)
Channel 3 - V
CC
(10V/div)
Channel 4 - Regulator Input Voltage (5V/div)
Soft Start @
COMP > 1.1V
OCP @
V
CC
> 8.4V
Duty Cycle = V
OUT
/ V
IN
0.27V / 3.54V = 7%
5.2%
Start-up @
V
CC
> 8.4V
Initial Pulse until V
> COMP + PWM Offset
Start-up @
V
CC
> 8.4V
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