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參數(shù)資料
| 型號： | CS5346-DQZ |
| 廠商： | CIRRUS LOGIC INC |
| 元件分類： | ADC |
| 中文描述： | 2-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PQFP48 |
| 封裝： | LEAD FREE, MS-022, LQFP-48 |
| 文件頁數(shù)： | 15/40頁 |
| 文件大小： | 402K |
| 代理商： | CS5346-DQZ |
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DS861PP2
CS5346
5.2.2
Master Mode
As a clock master, LRCK and SCLK will operate as outputs. LRCK and SCLK are internally derived from
MCLK with LRCK equal to Fs and SCLK equal to 64 x Fs as shown in Figure 8.
5.2.3
Slave Mode
In Slave Mode, SCLK and LRCK operate as inputs. The Left/Right clock signal must be equal to the sam-
ple rate, Fs, and must be synchronously derived from the supplied master clock, MCLK.
The serial bit clock, SCLK, must be synchronously derived from the master clock, MCLK, and be equal to
128x, 64x or 48x Fs, depending on the desired speed mode. Refer to Table 3 for required clock ratios.
5.3
High-Pass Filter and DC Offset Calibration
When using operational amplifiers in the input circuitry driving the CS5346, a small DC offset may be driven
into the A/D converter. The CS5346 includes a high-pass filter after the decimator to remove any DC offset
which could result in recording a DC level, possibly yielding clicks when switching between devices in a mul-
tichannel system.
The high-pass filter continuously subtracts a measure of the DC offset from the output of the decimation
filter. If the HPFFreeze bit (See “High-Pass Filter Freeze (Bit 1)” on page 31.) is set during normal operation,
the current value of the DC offset for the each channel is frozen and this DC offset will continue to be sub-
tracted from the conversion result. This feature makes it possible to perform a system DC offset calibration
by:
1. Running the CS5346 with the high-pass filter enabled until the filter settles. See the Digital Filter Char-
acteristics section for filter settling time.
2. Disabling the high-pass filter and freezing the stored DC offset.
A system calibration performed in this way will eliminate offsets anywhere in the signal path between the
calibration point and the CS5346.
Single-Speed
Double-Speed
Quad-Speed
SCLK/LRCK Ratio
48x, 64x, 128x
48x, 64x
Table 3. Slave Mode Serial Bit Clock Ratios
÷256
÷128
÷64
÷4
÷2
÷1
00
01
10
00
01
10
LRCK
SCLK
000
001
010
÷1
÷1.5
÷2
011
100
÷3
÷4
MCLK
FM Bits
MCLK Freq Bits
Figure 8. Master Mode Clocking
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| CS5346-DQZR | 功能描述:音頻數(shù)/模轉(zhuǎn)換器 IC 103dB 24Bit 192kHz Stereo Audio ADC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量: 分辨率:16 bit 接口類型:I2S, UBS 轉(zhuǎn)換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數(shù)量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel |
| CS5349-000 | 制造商:TE Connectivity 功能描述:4110-10-340812 |
| CS5349-BP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog-to-Digital Converter， 16-Bit |
| CS5349-BS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog-to-Digital Converter， 16-Bit |
| CS5349-KP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog-to-Digital Converter， 16-Bit |
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