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參數(shù)資料
| 型號： | CS5526-BSZ |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 13/30頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 20BIT W/4BIT LATCH 20SSOP |
| 標(biāo)準(zhǔn)包裝： | 66 |
| 位數(shù)： | 20 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 12.7mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-SSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個差分，單極；1 個差分，雙極 |
| 產(chǎn)品目錄頁面： | 755 (CN2011-ZH PDF) |
| 配用： | 598-1014-ND - EVAL BOARD FOR CS5526 |
| 其它名稱： | 598-1108-5 |
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CS5525 CS5526
20
DS202F5
the input signal can be reduced to the point in
which the gain register reaches its upper limit of 2.0
(decimal) [FFFFFF Hex] (this is most likely to oc-
cur with an input signal approximately 1/2 the
nominal range). Alternatively, the input signal can
be increased to a point in which the modulator
reaches its one’s density upper limit of 80% (this is
most likely to occur with an input signal approxi-
mately 1.5 times the nominal range). Also, for full
scale inputs larger than the nominal full scale value
of the range selected, there is some voltage at
which the various internal circuits may saturate due
to limited amplifier headroom (this is most likely to
occur on the 100 mV range setting when NBV = -
1.8 V).
Analog Output Latch Pins
The A3-A0 pins of the converters mimic the D23-
D20 bits of the configuration register. A3-A0 can
be used to control multiplexers and other logic
functions outside the converter. The outputs can
sink or source at least 1 mA, but it is recommended
to limit drive currents to less than 20
A to reduce
self-heating of the chip. These outputs are powered
from VA+, hence, their output voltage for a logic 1
will be limited to the VA+ voltage.
Serial Port Interface
The CS5525/26 serial interface consist of four pins,
SCLK, SDO, SDI, and CS. The CS pin must be
held low (logic 0) before SCLK transitions can be
recognized by the port logic. The SDO output will
be held at high impedance any time CS is a logic 1.
If the CS pin is tied low, the port can function as a
three wire interface.
The SCLK input is designed with a Schmitt-trigger
input to allow an optoisolator with slower rise and
fall times to directly drive the pin.
The SDO output is capable of sinking or sourcing
up to 5 mA to directly drive an optoisolator LED.
SDO will have less than a 400 mV loss in the drive
voltage when sinking or sourcing 5 mA.
Serial Port Initialization
The serial port is initialized to the command mode
whenever a power-on reset is performed inside the
converter, when the port initialization sequence is
completed, or whenever a command byte, data
word sequence is completed. The port initialization
sequence involves clocking 15 (or more) bytes of
all 1's, followed by one byte with the following bit
contents (11111110). This sequence places the
chips in the command mode where it waits for a
valid command.
Performing Conversions (With PF bit = 0)
Setting the SC (Single Conversion) bit of the com-
mand word to a logic 1 with the CB bit = 1, all other
command bits = 0, the CS5525/CS5526 will per-
form one conversion. At the completion of the con-
version the DF (Done Flag) bit of the configuration
register will be set to a logic 1. The user can read
the configuration register to determine if the DF bit
is set. If DF has been set, a command can be issued
to read the conversion data register to obtain the
conversion data word. The DF bit of the configu-
ration register will be cleared to logic 0 when the
data register, the gain register, the offset register, or
the set-up registers are read. Reading only the con-
figuration register will not clear the DF flag bit.
If an SC command is issued to the converters while
they are performing a conversion, the filter will re-
start a convolution cycle to perform a new conver-
sion.
Performing Conversions (With PF bit = 1)
Setting the PF bit of the configuration register to a
logic 1 enables the SDO output pin to behave as a
flag signal whenever conversions are completed.
This eliminates the need for the user to read the DF
flag bit of the configuration register to determine if
the conversion data word is available.
If the SC (Single Conversion) command is issued
(SC = 1, CB= 1, all other command bits = 0) the
SDO pin will go low at the completion of a conver-
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參數(shù)描述 |
|---|---|
| CS5526-BSZR | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC IC 20Bit Delta Sigma Multi-Range ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| CS5527-000 | 功能描述:電線鑒定 HT-SCE-1K-1/8-2.0-9-CS7822 RoHS:否 制造商:TE Connectivity / Q-Cees 產(chǎn)品:Labels and Signs 類型: 材料:Vinyl 顏色:Blue 寬度:0.625 in 長度:1 in |
| CS5528 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:16-bit or 24-bit, 2/4/8-channel ADCs with PGIA |
| CS5528-AP | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Cirrus Logic 功能描述: |
| CS5528-AS | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 8-Ch 24-Bit Delta Sigma Mult-range ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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