參數(shù)資料
型號(hào)： CS5526-BSZ
廠商： Cirrus Logic Inc
文件頁數(shù)： 9/30頁
文件大?。?/td> 0K
描述： IC ADC 20BIT W/4BIT LATCH 20SSOP
標(biāo)準(zhǔn)包裝： 66
位數(shù)： 20
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 12.7mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 20-SSOP（0.209"，5.30mm 寬）
供應(yīng)商設(shè)備封裝： 20-SSOP
包裝： 管件
輸入數(shù)目和類型： 1 個(gè)差分，單極；1 個(gè)差分，雙極
產(chǎn)品目錄頁面： 755 (CN2011-ZH PDF)
配用： 598-1014-ND - EVAL BOARD FOR CS5526
其它名稱： 598-1108-5
CS5525 CS5526
DS202F5
17
The offset and gain calibration steps each take one
conversion cycle to complete. At the end of the cal-
ibration step, the calibration control bits will be set
back to logic 0, and the DF (Done Flag) bit will be
set to a logic 1. For the combination self-calibra-
tion (CC2-CC0= 011; offset followed by gain), the
calibration will take two conversion cycles to com-
plete and will set the DF bit after the gain calibra-
tion is completed. The DF bit will be cleared any
time the data register, the offset register, the gain
register, or the setup register is read. Reading the
configuration register alone will not clear the DF
bit.
Self Calibration
The CS5525/26 offer both self offset and self gain
calibrations. For the self-calibration of offset in the
25 mV, 55 mV, and 100 mv ranges, the converter
internally ties the inputs of the instrumentation am-
plifier together and routes them to the AIN- pin as
shown in Figure 10. For proper self-calibration of
offset to occur in the 25 mV, 55 mV, and 100 mV
ranges, the AIN- pin must be at the proper com-
mon-mode-voltage (i.e. AIN- = 0V, NBV must be
between -1.8 V to -2.5 V). For self-calibration of
offset in the 1.0 V, 2.5 V, and 5 V ranges, the inputs
of the modulator are connected together and then
routed to the VREF- pin as shown in Figure 11.
For self-calibration of gain, the differential inputs
of the modulator are connected to VREF+ and
Table 3.
Table 4. Offset and Gain Registers
Offset Register
One LSB represents 2-24 proportion of the input span (bipolar span is 2 times unipolar span)
Offset and data word bits align by MSB (bit MSB-4 of offset register changes bit MSB-4 of data)
Gain Register
The gain register span is from 0 to (2-2-23). After Reset the MSB = 1, all other bits are 0.
MSB
LSB
Register
Sign
2-2
2-3
2-4
2-5
2-6
2-19
2-20
2-21
2-22
2-23
2-24
Reset (R)
0
000000
MSB
LSB
Register
20
2-1
2-2
2-3
2-4
2-5
2-18
2-19
2-20
2-21
2-22
2-23
Reset (R)
1
0
000000
≈
AIN+
AIN-
S1
OPEN
S2
CLOSED
+
-
X20
+
-
Figure 10. Self Calibration of Offset (Low Ranges).
AIN+
AIN-
S1
OPEN
+
-
X20
+
-
S2
OPEN
S4
CLOSED
VREF-
S3
CLOSED
Figure 11. Self Calibration of Offset (High Ranges).
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