參數資料
型號： CS61577-IP1
廠商： Electronic Theatre Controls, Inc.
英文描述： T1/E1 LINE INTERFACE
中文描述： 的T1/E1線路接口
文件頁數： 5/44頁
文件大?。?/td> 632K
代理商： CS61577-IP1
E1 SWITCHING CHARACTERISTICS
(TA = -40
°
C to 85
°
C; TV+, RV+ = 5.0V
±
5%;
GND = 0V; Inputs: Logic 0 = 0V, Logic 1 = RV+; See Figures 1, 2, & 3)
Parameter
Symbol
f
c
f
tclk
t
pwh2
/t
pw2
f
aclki
t
pwh1
/t
pw1
t
r
t
f
t
su2
t
h2
t
su1
t
su1
t
su1
t
h1
t
h1
t
h1
Min
-
-
40
-
45
-
-
25
25
100
100
100
100
100
100
Typ
Max
-
-
60
-
55
85
85
-
-
-
-
-
-
-
-
Units
MHz
MHz
%
MHz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Crystal Frequency
TCLK Frequency
TCLK Duty Cycle for LEN2/1/0 = 0/0/0
ACLKI Frequency
RCLK Duty Cycle
Rise Time, All Digital Outputs
Fall Time, All Digital Outputs
TPOS/TNEG (TDATA) to TCLK Falling Setup Time
TCLK Falling to TPOS/TNEG (TDATA) Hold Time
RPOS/RNEG Valid Before RCLK Falling
RDATA Valid Before RCLK Falling
RPOS/RNEG Valid Before RCLK Rising
RPOS/RNEG Valid After RCLK Falling
RDATA Valid After RCLK Falling
RPOS/RNEG Valid After RCLK Rising
(Note 25)
8.192000
2.048
50
2.048
50
-
-
-
-
194
194
194
194
194
194
(Note 32)
(Note 26)
(Note 27)
(Note 28)
(Note 28)
(Note 29)
(Note 30)
(Note 31)
(Note 29)
(Note 30)
(Note 31)
T1 SWITCHING CHARACTERISTICS
(TA = -40
°
C to 85
°
C; TV+, RV+ = 5.0V
±
5%;
GND = 0V; Inputs: Logic 0 = 0V, Logic 1 = RV+; See Figures 1, 2, & 3)
Parameter
Symbol
f
c
f
tclk
f
aclki
t
pwh1
/t
pw1
t
r
t
f
t
su2
t
h2
t
su1
t
su1
t
su1
t
h1
t
h1
t
h1
Min
-
-
-
45
-
-
25
25
150
150
150
150
150
150
Typ
Max
-
-
-
55
85
85
-
-
-
-
-
-
-
-
Units
MHz
MHz
MHz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Crystal Frequency
TCLK Frequency
ACLKI Frequency
RCLK Duty Cycle
Rise Time, All Digital Outputs
Fall Time, All Digital Outputs
TPOS/TNEG (TDATA) to TCLK Falling Setup Time
TCLK Falling to TPOS/TNEG (TDATA) Hold Time
RPOS/RNEG Valid Before RCLK Falling
RDATA Valid Before RCLK Falling
RPOS/RNEG Valid Before RCLK Rising
RPOS/RNEG Valid After RCLK Falling
RDATA Valid After RCLK Falling
RPOS/RNEG Valid After RCLK Rising
Notes: 25. Crystal must meet specifications described in CXT6176/CXT8192 data sheet.
26. ACLKI provided by an external source or TCLK.
27. RCLK duty cycle will be 62.5% or 37.5% when jitter attenuator limits are reached.
28. At max load of 1.6 mA and 50 pF.
29. Host Mode (CLKE = 1).
30. Extended Hardware Mode.
31. Hardware Mode, or Host Mode (CLKE = 0)
32. The transmitted pulse width does not depend on the TCLK duty cycle.
(Note 25)
6.176000
1.544
1.544
50
-
-
-
-
274
274
274
274
274
274
(Note 26)
(Note 27)
(Note 28)
(Note 28)
(Note 29)
(Note 30)
(Note 31)
(Note 29)
(Note 30)
(Note 31)
CS61577
DS155PP2
5
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