FN2784.5 March 17, 2006 AC Test Circuit (4) TAHWL A0/CS Setup to WR 0- ns (5) TWHAX A0/CS Hold after WR 5- 0- ns (6) TWLWH WR Pulse Width 165 -" />
參數(shù)資料
型號: CS82C59A-1296
廠商: Intersil
文件頁數(shù): 10/22頁
文件大?。?/td> 0K
描述: IC CTRL INTERRUPT 12.5MHZ 28PLCC
標(biāo)準(zhǔn)包裝: 750
控制器類型: CMOS 優(yōu)先中斷控制器
接口: 系統(tǒng)總線
電源電壓: 4.5 V ~ 5.5 V
電流 - 電源: 1mA
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 28-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 28-PLCC(11.51x11.51)
包裝: 帶卷 (TR)
18
FN2784.5
March 17, 2006
AC Test Circuit
(4) TAHWL
A0/CS Setup to WR
0-
ns
(5) TWHAX
A0/CS Hold after WR
5-
0-
ns
(6) TWLWH
WR Pulse Width
165
-
95
-
60
-
ns
(7) TDVWH
Data Setup to WR
240
-
160
-
70
-
ns
(8) TWHDX
Data Hold after WR
5-
0-
ns
(9) TJLJH
Interrupt Request Width Low
100
-
100
-
40
-
ns
(10) TCVlAL
Cascade Setup to Second or Third INTA (Slave
Only)
55
-
40
-
30
-
ns
(11) TRHRL
End of RD to next RD, End of INTA (within an
INTA sequence only)
160
-
160
-
90
-
ns
(12) TWHWL
End of WR to next WR
190
-
190
-
60
-
ns
(13) TCHCL
(Note 1)
End of Command to next command (not same
command type), End of INTA
sequence to next INTA sequence
500
-
400
-
90
-
ns
TIMING RESPONSES
(14) TRLDV
Data Valid from RD/INTA
-
160
-
120
-
40
ns
1
(15) TRHDZ
Data Float after RD/INTA
5
100
5
85
5
22
ns
2
(16) TJHlH
Interrupt Output Delay
-
350
-
300
-
90
ns
1
(17) TlALCV
Cascade Valid from First INTA
(Master Only)
-
565
-
360
-
50
ns
1
(18) TRLEL
Enable Active from RD or INTA
-
125
-
100
-
40
ns
1
(19) TRHEH
Enable Inactive from RD or INTA
-60-
50
-
22
ns
1
(20) TAHDV
Data Valid from Stable Address
-
210
-
200
-
60
ns
1
(21) TCVDV
Cascade Valid to Valid Data
-
300
-
200
-
70
ns
1
NOTE:
1. Worst case timing for TCHCL in an actual microprocessor system is typically greater than the values specified for the 82C59A,
(i.e. 8085A = 1.6
s, 8085A -2 = 1s, 80C86 = 1s, 80C286 -10 = 131ns, 80C286 -12 = 98ns).
AC Electrical Specifications
VCC = +5.0V ±10%, GND = 0V, TA = Operating Temperature Range (Continued)
SYMBOL
PARAMETER
5MHz
8MHz
12.5MHz
UNITS
TEST
CONDITIONS
MIN
MAX
MIN
MAX
MIN
MAX
TEST CONDITION DEFINITION TABLE
TEST
CONDITION
V1
R1
R2
C1
1
1.7V
523
Open
100pF
2VCC
1.8k
1.8k
50pF
V1
R1
R2
C1
(NOTE)
OUTPUT FROM
DEVICE UNDER
TEST
POINT
NOTE: Includes stray and jig capacitance.
82C59A
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