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參數(shù)資料
| 型號(hào)： | CXA1977R |
| 廠商： | Sony Corporation |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | Low Power 5V RS232 Dual Driver/Receiver with 0.1?μF Capacitors; Package: SO; No of Pins: 16; Temperature Range: -40?°C to 85?°C |
| 中文描述： | 電可擦除可編程邏輯器件 |
| 文件頁數(shù)： | 10/16頁 |
| 文件大?。?/td> | 273K |
| 代理商： | CXA1977R |
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CXA1977R
7. Clock input (CLK)
TTL input. Clock line wiring should be the shortest possible while distanced from other signal lines to avoid
affecting them.
This IC is 2-step parallel type A/D converter. Accordingly an external sample-and-hold circuit (SH) is
necessary. However the timing between this SH circuit output waveform (A/D converter analog input
waveform) and the A/D converter clock timing requires attention. In the relation between A/D converter
clock and the A/D converter analog input signal, with the timing T
H
of the rising edge of A/D converter
clock, the upper comparator compares the input signal and the reference voltage to latch the results. After
that, with the timing T
L
of the falling edge of A/D converter clock, the lower comparator compares the input
signal and reference signal to latch the results. (Strictly speaking, the sampling delay
t
SH
is in T
H
and the
sampling delay
t
SL
is in T
L
.)
In this A/D converter, the lower comparator features a length of ±32mV (±16LSB) redundance in relation to
the upper comparator. At the timing when the lower comparator compares input signal and reference
signal to latch at the timing T
L
, it is necessary to have the SH output settling performed. But at the timing
when the upper comparator compares input signal and reference voltage to latch at the timing T
H
, as long
as the SH output is within the ±32mV range to the final settling value, digital correction applies, A/D
conversion precisely occurs. As seen from the above, A/D converter clock rise and fall timing versus SH
output waveform should be duly considered. For the clock high level time
t
PWH
and low level time
t
PWL
, set
to a value in excess of the time indicated for the respective operating conditions.
Output data is synchronously with the clock rising edge.
For details on timing, refer to the Timing Chart.
8. MINV input (MINV)
Digital output polarity inversion control pin of D9 (MSB).
TTL input. At open, turns to high level input.
For correspondence with analog input voltage and output data code, refer to the Output Formula Chart.
9. LINV input (LINV)
Digital output polarity inversion control pin of D8 to D0 (LSB).
TTL input. At open, turns to high level input.
For correspondence with analog input voltage and output data code, refer to the Output Formula Chart.
10. Output enable (ENABLE)
3-state control pin of digital output (D0 to D9, UNDER, OVER)
TTL input. At open, turns to high level input. At that time digital output turns all to high impedance.
11. Power save input (PS)
Power save control pin of internal circuit.
TTL input. At open, turns to high level input.
To set to power save mode, turn both PS and ENABLE to high level input.
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