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CXD1199AQ
2-2-16. HSTPRM (host parameter) register
The command parameters from the host are read out from this register. The register has an 8-byte FIFO
configuration.
2-2-17. HSTCMD (host command) register
The command from the host are read out from this register.
REG
DRVIF
CONFIG 1
CONFIG 2
DECCTL
DLADR-L
DLADR-M
DLADR-H
CHPCTL
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
“L”
EMPHASIS
Sub CPU write registers
INTMSK
CLRCTL
CLRINT
HXFR-L
HXFR-H
HADR-L
HADR-M
DADRC-L
DADRC-M
DADRC-H
HIFCTL
RESULT
ADPMNT
RTCI
ADR
00
01
02
03
04
05
06
bit7
C2PO L 1st
“L”
“L”
EN DLADR
bit7
bit15
“L”
SM MUTE
“L”
DRV OVRN
CHP RST
DRV OVRN
bit7
DIS HXFRC
bit7
bit15
bit7
bit15
“L”
“L”
“L”
“L”
“L”
bit7
“L”
RTADP EN
“L”
bit6
LCH LOW
XSLOW
“L”
ECC STR
bit6
bit14
“L”
RT MUTE
“L”
DEC TOUT
CLR BUSY
DEC TOUT
bit6
“L”
bit6
bit14
bit6
bit14
“L”
“L”
“L”
“L”
“L”
bit6
“L”
bit16
“L”
bit5
BCK RED
PRTY CTL
SPE CTL
MODE SEL
bit5
bit13
“L”
CDDA MUTE
“L”
RSLT EMPT
CLR RSLT
RSLT EMPT
bit5
“L”
bit5
bit13
bit5
bit13
“L”
“L”
“L”
“L”
“L”
bit5
“L”
bit15
“L”
“L”
bit4
BCK MD1
RAM SZ1
SPM CTL
FORM SEL
bit4
bit12
“L”
CD-DA
“L”
RTADP END
RTADP CLR
RTADP END
bit4
HADR bit16
bit4
bit12
bit4
bit12
“L”
“L”
“L”
“L”
“L”
bit4
“L”
bit14
“L”
BIT LNGTH
bit3
BCK MD0
RAM SZ0
SM BF2
AUTO DIST
bit3
bit11
“L”
SW OPEN
“L”
HDMA CMP
“L”
HDMA CMP
bit3
bit11
bit3
bit11
bit3
bit11
“L”
“L”
“L”
“L”
“L”
bit3
“L”
bit13
“L”
“L”
bit2
LSB 1st
9 bit RAM
DAMIX EN
DEC MD2
bit2
bit10
“L”
RPS TART
“L”
DEC INT
“L”
DEC INT
bit2
bit10
bit2
bit10
bit2
bit10
“L”
“L”
“L”
“L”
HINT #2
bit2
“L”
bit12
“L”
FS
bit1
“L”
CLK DIS
DACO DIS
DEC MD1
bit1
bit9
“L”
DBL SPD
“L”
HST CMND
“L”
HST CMND
bit1
bit9
bit1
bit9
bit1
bit9
“L”
“L”
“L”
“L”
HINT #1
bit1
“L”
bit11
“L”
“L”
bit0
“L”
HCLK DIS
“L”
DEC MD0
bit0
bit8
bit16
“L”
“L”
HCR ISD
RE SYNC
HCR ISD
bit0
bit8
bit0
bit8
bit0
bit8
bit16
“L”
“L”
“L”
HINT #0
bit0
“L”
bit10
“L”
S/M