參數(shù)資料
型號(hào)： CXD1856R
廠商： Sony Corporation
英文描述： MPEG1 Decoder
中文描述： MPEG1解碼器
文件頁(yè)數(shù)： 20/31頁(yè)
文件大小： 395K
代理商： CXD1856R
– 20 –
CXD1856Q/R
7) When executing read commands, register data output starts from the 3rd output byte (bit 16). All earlier
output data is invalid data. Access shifts to a new register each time the output for one register (2 bytes) is
finished. For example, in case of the command 0x10, the byte data specified by the 2nd input byte is output
to the 3rd output byte, the other byte data in the same register is output to the 4th byte, and the byte data
specified by the 4th input byte is output to the 5th output byte.
8) The "first bit" column indicates whether LSB first or MSB first processing is performed for input or output of
the 2nd and subsequent bytes. This specification does not apply to the 1st byte (command). Commands
are normally LSB first. If LSB first is specified, processing is performed in the order where the initial bit in
each byte is LSB and the final bit is MSB. This order is reversed for MSB first. Note that for registers, bit 15
noted in the Register Manual is MSB and bit 0 is LSB.
4-2. DRAM Interface Function
The applicable DRAMs are speed version 70 devices (RAS access time (Trac) of 70ns or less) with the fast
page mode function.
When the total capacity of the external DRAM is 4 Mbits, use a 2CAS type DRAM with a configuration of 256
Kwords
×
16 bits. When the total capacity is 8 Mbits, use two 2CAS type DRAMs with a configuration of 256
Kwords
×
16 bits or 512 Kwords
×
8 bits.
Refresh is performed automatically using RAS-only-refresh. External control is not necessary.
The DRAM is divided into the image frame memory, audio bit stream buffer, video bit stream buffer, user
data and on-memory register areas.
The user data area can be used freely by the user, and CD-ROM decoded output can also be transferred to
this area. This area can be used to store video CD PSD, etc.
The desired DRAM areas can be accessed from the control microcomputer via the registers.
4-3. CD-ROM Decoder Function
CD signal processor LSI interface
The CD-ROM decoder has a CD signal processor LSI (CD-DSP) interface which directly interfaces the serial
data output from the CD-DSP. This interface supports a wide variety of input formats to enable connection
with general CD-DSP.
CD-ROM data decoding (supports CD-ROM XA format mode2, form1 and form2)
CD-ROM data input from the CD-DSP supports CD-ROM XA format (mode2, form1 and form2).
Input CD-ROM data is decoded by the CD-ROM decoder block. Also, the CD-DA signal input from the CD-
DSP can be output directly from the audio interface.
The CD-ROM decoder has the following decoding and data transfer operating modes. The real-time
correction and write-only modes facilitate the loading of video CD PSD to the external DRAM, etc.
1) Auto transfer mode
The MPEG pack data within one sector of the video CD is automatically transferred to the system
decoder, where the audio stream sector or video stream sector can be decoded. This mode transfers
2324 bytes counted from the initial byte of user data within one sector to the system decoder.
2) Real-time correction mode
This mode executes error detection and correction processing for mode2, form1 sectors. The 2048 bytes
of user data within the error processed sector are transferred to the user area of the external DRAM. The
4 bytes of header information within the sector can also be loaded in the on-memory register within the
DRAM.
3) Write-only mode
This mode transfers the 2340 bytes of header, subheader and user data within one sector to the user area
of the external DRAM. When a form1 sector is input, error detection and correction processing is
performed and then the data is transferred to the buffer memory. When a form2 sector is input, the data is
transferred as is.
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