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參數(shù)資料
| 型號： | CXD2073S |
| 廠商： | Sony Corporation |
| 英文描述： | Digital Comb Filter (NTSC) |
| 中文描述： | 數(shù)字梳狀濾波器（NTSC制式） |
| 文件頁數(shù)： | 3/11頁 |
| 文件大?。?/td> | 160K |
| 代理商： | CXD2073S |
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CXD2073Q
Pin Description
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
ADIN
ADVS
ADVD
ACO
NC
DAVD
AYO
DAVS
VRF
VG
VB
IRF
INIT
MOD2
MOD1
APCN
TST3
DV
SS
DV
DD
NC
DV
DD
DV
SS
TST2
TST1
FIN
CKSL
CPO
VCV
PLVD
PLVS
CLPEN
CLPO
I
—
—
O
—
—
O
—
I
O
O
O
I
I
I
I
O
—
—
—
—
—
O
I
I
I
O
I
—
—
I
O
Comb filter analog input (A/D converter input)
Analog ground for A/D converter
Analog power supply for A/D converter (+5V)
Analog chroma signal output
Leave this pin open.
Analog power supply for D/A converter (+5V)
Analog luminance signal output
Analog ground for D/A converter
D/A converter reference voltage setting. Sets the full-scale value for D/A converter.
Connect to DAVD via a capacitor of approximately 0.1μF.
Connect to DAVS via a capacitor of approximately 0.1μF.
Connect a resistor of 16 times (16R) that of the output resistor "R" of AYO pin.
Test. Normally, fix to Low.
Y/C separation status setting pins
MOD2 MOD1
L
L
Adaptive processing mode
L
H
BPF separation fixed mode
H
L
Y through mode
H
H
Simple comb mode
Aperture compensation switching
L: Aperture compensation OFF
H: Aperture compensation ON
Test. Normally, leave this pin open.
Digital ground
Digital power supply (+5V)
Leave this pin open.
Digital power supply (+5V)
Digital ground
Test. Normally, leave this pin open.
Test. Normally, fix to Low.
Clock input. Input burst-locked clock. Input fsc when the PLL is used. Input 4fsc
when the PLL is not used.
PLL control.
L: When the PLL is not used. The 4fsc clock input to FIN is supplied internally.
H:When the PLL is used. The 4fsc clock from VCO oscillation output is
supplied internally.
Phase comparison output for the internal PLL. Leave open when the PLL is not
used.
VCO oscillation control voltage input for the internal PLL. Connect to PLVS when
the PLL is not used.
PLL analog power supply (+5V)
PLL analog ground
Clamp enable
L: Clamp function is enabled. Set to L when the internal clamp is used.
H: Clamp function is disabled. Set to H when the internal clamp is not used.
Connect to ADIN when clamp circuit is used.
Leave this pin open when clamp circuit is not used.
Symbol
I/O
Description
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