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參數(shù)資料
| 型號(hào)： | CXD2073S |
| 廠商： | Sony Corporation |
| 英文描述： | Digital Comb Filter (NTSC) |
| 中文描述： | 數(shù)字梳狀濾波器（NTSC制式） |
| 文件頁(yè)數(shù)： | 7/11頁(yè) |
| 文件大?。?/td> | 160K |
| 代理商： | CXD2073S |
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CXD2073Q
Notes on Operation
Power supply, ground
Separate the analog and digital systems around the device to reduce noise effect. Both analog and digital
V
DD
are respectively bypassed to V
SS
as close to these V
DD
and V
SS
pins as possible through ceramic
capacitors of approximately 0.1μF.
Also, layout the power supply and ground pattern of the board substrate as wide as possible to lower
impedance.
Clock
Use the burst-locked clock. Separate the clock line on the board substrate as far as possible from analog-
related pins, analog power supply, and analog ground.
ADIN (analog input signal)
(1) Low impedance drive
The input signal to ADIN (Pin 1) should be driven at the low impedance and its wiring should be as short
as possible.
(2) Input level
Set the input signal peak-to-peak value VPP to 1.75V or less. Additionally, VPP is recommended to be
1.3V or more since the A/D converter input dynamic range should be made as large as possible.
VPP
2.60V (Reference top voltage typical value for internal A/D converter)
0.67V (Sync tip clamp level)
0.52V (Reference bottom voltage typical value for internal A/D converter)
C
B
A
The DC level at the ADIN pin is as shown in the diagram above when the internal sync tip clamp is used.
Labeling the internal D/A converter AYO output full-scale voltage as VFS, the correspondence between
the ADIN pin voltage and AYO output pin voltage (DC level) is as follows;
DC voltage at point A
→
0 [V]
DC voltage at point B
→
AYO maximum output voltage [V]
DC voltage at point C
→
VFS [V]
The VFS is the AYO output voltage generated when the voltage equivalent to the point C is input.
Internal delay
The delay from the internal A/D converter to the D/A converter output is 21.5 clocks +
α
ns (
α
: D/A converter
analog output delay = approximately 20ns).
The 21.5 clocks are the sum of the clocks shown below;
A/D converter: 3.5 clocks (“0.5” is for fetching the data at the fall of the clock.)
Internal logic : 17 clocks
D/A converter: 1 clock
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