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參數(shù)資料
| 型號： | CXD2442Q |
| 廠商： | Sony Corporation |
| 英文描述： | Timing Generator for LCD Panels |
| 中文描述： | 時序發(fā)生器的液晶面板 |
| 文件頁數(shù)： | 13/70頁 |
| 文件大?。?/td> | 9533K |
| 代理商： | CXD2442Q |
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CXD2442Q
Description of Operation
Sync signal input
The HSYNC and VSYNC input pins support both separate SYNC and CSYNC. When using the CXD2442Q
with CSYNC input, input CSYNC to both pins. (However, CSYNC input is supported only when using the built-
in double-speed controller.)
Clock input
The CXD2442Q has two clock input pin systems to support two types of PLL circuits
(1) CKI1 pin
A PLL circuit is comprised by the built-in phase comparator and an external VCO circuit. CKI1 is the clock
input pin when using this system, and supports the NTSC and PAL double-speed display modes (systems
which use the built-in double-speed controller). The PLL clock for this system is adjusted by setting the
RPD and FPD transition points so that they fall at the center of the windows as shown in the diagram
below. (See the Application Circuit.)
(2) CKI2 pin
This is the clock input pin when using an external PLL IC. The 1/N frequency divider output is output from
the HDN pin for the PLL IC. The HDN polarity at this time is set by the serial data HPOL.
The HDN width is calculated using the frequency division ratio N/2.
AC driving of LCD panels for no signal
The following measures have been adopted to allow AC driving of LCD panels even when there is no signal.
Horizontal direction pulse
The PLL is set to free running status. Therefore, the frequency of the horizontal direction pulse is
dependent on the PLL free running frequency.
Vertical direction pulse
The number of lines is counted by an internal counter (AUX-VD COUNTER) and the vertical direction
pulses (VST, FRP) are output at a specified cycle. For the CXD2442Q, no signal (free running) status is
judged if there is no VSYNC input for longer than the following (free running detection) periods.
b
500ns
b
Output waveform during PLL lock
a
a
HSYNC
RPD
FPD
N f
H
HSYNC
HDN
N/2 f
H
HPOL: L
HPOL: H
Mode
NTSC
PAL
Other
V cycle for no signal
263H
313H
650H
Free running detection
468H
900H
Note)
NTSC and PAL modes are the modes when using the built-in double-speed controller.
f
H
: Master clock cycle (1 dot)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CXD2443Q | Timing Generator for LCD Panels |
| CXD2450R | Timing Generator For Progressive Scan CCD Image Sensor(步進掃描CCD圖像傳感器的定時信號發(fā)生器) |
| CXD2452R | Timing Generator for Progressive Scan CCD Image Sensor |
| CXD2453Q | Timing Generator for LCD Panels |
| CXD2457R | Timing Generator for Progressive Scan CCD Image Sensor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CXD2443Q | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Timing Generator for LCD Panels |
| CXD2450R | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Timing Generator for Progressive Scan CCD Image Sensor |
| CXD2452R | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Timing Generator for Progressive Scan CCD Image Sensor |
| CXD2453Q | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Timing Generator for LCD Panels |
| CXD2457R | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Timing Generator for Progressive Scan CCD Image Sensor |
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