參數(shù)資料
型號: CXD2460R
廠商: Sony Corporation
英文描述: Timing Generator for Progressive Scan CCD Image Sensor
中文描述: 時序發(fā)生器傳感器逐行掃描CCD圖像
文件頁數(shù): 18/36頁
文件大?。?/td> 341K
代理商: CXD2460R
Detailed description
– 18 –
D14
to
D15
IDSEL
D23
to
D29
FVFS
D12
SGXEN
0: Normal operation
1: XSGA and XSGB are output from the HRO and FRO pins.
Note that the output pulse amplitude is V
SS
to V
DD
a.
These bits select the pulse output from the ID pin.
XSUB: Inverted SUB pulse output at the amplitude of V
SS
to V
DD
a
D13
EXSG
0: VT (readout clock) is added to V2A, V2B and V3 as normal.
1: VT is not added to V2A, V2B and V3.
During readout, only the modulation necessary for readout is performed.
Note that this setting has priority over mode control data NSG (D14).
D16
VTXEN
0: Checksum is not performed and the checksum data is invalid. (However, dummy data must be
set in the CHKSUM register.)
1: Checksum is performed. This data is reflected even if the checksum results are NG.
D17
CHKSUM
0: The EXP pulse is output from the EXP pin.
1: High is indicated if the checksum results from the EXP pin are OK, and low if the results are NG.
This pulse is output at the rise of SEN, and reset high again at the fall of SEN. This pulse has
priority over mode control data EXP.
D18
STATUS
D14
0
1
D15
0
ID pulse output
XSUB pulse output
1
WEN pulse output
ID pulse output
Input "0".
These bits set the high-speed sweep period (unit: H) in FS mode.
The high-speed sweep is perfomed for 8 lines for every 1H when FINE = 1, and 20 lines for every
1H when FINE = 0.
D19
to
D22
MSB
LSB
D29
D28
D27
D26
D25
D24
D23
CXD2460R
CTGRY: System setting data
0: Internal SSG (Sync Signal Generator) functions operate to generate FRO and HRO.
1: Internal SSG functions are stopped, and the FRO and HRO pulses are fixed to low.
Note that the STB setting has priority. Set SGXEN to "1" in the case of input of a CXD2460R
sync signal from the outside.
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