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參數(shù)資料
| 型號： | CXD2467AQ |
| 廠商： | Sony Corporation |
| 英文描述： | Digital Signal Driver/Timing Generator |
| 中文描述： | 數(shù)字信號驅(qū)動器/時序發(fā)生器 |
| 文件頁數(shù)： | 30/38頁 |
| 文件大小： | 529K |
| 代理商： | CXD2467AQ |
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CXD2467AQ
(n) FRI: Free-running cycle setting
When VSYNC has not been input for a specified period, a judgment of "no signal" is made to allow AC driving
of LCD panels even when there is no signal. In this case, a vertical start pulse and FRP pulse are output at a
specified cycle (free-running operation). The period until a judgment of "no signal" is made and the VST pulse
cycle during free-running operation are set in FRI10 (MSB) to FRI0 (LSB). The initial value is 7FFh (2048H
cycle).
(o) MBK0 and MBK1: Decimation operation settings
This sets the decimation operation which decimates the display lines at a specified ratio. This IC has two built-
in modes: 2/14-line decimation and 1/4-line decimation. MBK0 turns decimation operation on and off, and
MBK1 selects the mode. Decimation is not performed when MBK0 = 0h, and is performed when MBK0 = 1h.
Also, 2/14-line decimation is performed when MBK1 = 0h, and 1/4-line decimation when MBK1 = 1h. The initial
values are MBK0 = 0h and MBK1 = 0h (no decimation).
(p) SLDS: Test data
This is test data. Set to 0h. The initial value is 0h.
(q) IRP: IRACT block frequency divider frequency division ratio setting
Like the PLL counter, this sets the frequency division ratio of the 1/N frequency divider for phase comparison.
The value of (total number of dots in one horizontal period N) – 1 is set in IRP11 (MSB) to IRP0 (LSB). The
frequency division ratio can be set up to 4096. However, only even numbers can be set for the value of N. The
initial value is 697h (N = 1688).
(r) SLHR: IRACT block frequency divider reset setting
This sets whether the IRACT block frequency divider is reset by the HSYNC input to HDIN2. The frequency
divider is reset when 0h, and not reset when 1h. The initial value is 0h (reset).
(s) IRU/IRD: IRACT pulse settings
The IRACT pulse rise position within one horizontal period is set in IRU11 (MSB) to IRU0 (LSB), and the fall
position in IRD11 (MSB) to IRD0 (LSB) relative to the HSYNC input to HDIN2. The IRACT block frequency
divider reset timing is used as the reference (all 0). Also, the least significant bit is ignored, so setting is in 2-
dot units. The initial values are IRU = 080h and IRD = 000h.
Note)
The above setting values may be invalid in certain cases. (For example, settings which exceed the
number of clocks in 1H or number of lines in 1V of the input signal, etc.) Normal pulses will not be
output in these cases, so be sure to refer to the setting examples on the following page when making
the settings.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CXD2467Q | Digital Signal Driver/Timing Generator |
| CXD2470R | Timing Generator for Frame Readout CCD Image Sensor |
| CXD2475TQ | Reference Voltage and Driver IC for LCD |
| CXD2492R | RES, WW 1W 4.02 OHM 1% 90PPM |
| CXD2497R | Timing Generator for Frame Readout CCD Image Sensor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CXD2467Q | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Digital Signal Driver/Timing Generator |
| CXD2470R | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Timing Generator for Frame Readout CCD Image Sensor |
| CXD2475TQ | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Reference Voltage and Driver IC for LCD |
| CXD2480R | 制造商:Sony Batteries 功能描述: |
| CXD2492R | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Timing Generator for Frame Readout CCD Image Sensor |
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