參數(shù)資料
型號(hào): CXD2507AQ
廠商: Sony Corporation
元件分類: 數(shù)字信號(hào)處理
英文描述: CD Digital Signal Processor
中文描述: CD數(shù)字信號(hào)處理器
文件頁數(shù): 8/38頁
文件大?。?/td> 375K
代理商: CXD2507AQ
– 8 –
CXD2507AQ
2) CLOK, DATA, XLAT, CNIN, SQCK EXCK pins
(V
DD
= AV
DD
= 5.0V ± 5%, V
SS
= AV
SS
= 0V, Topr = –20 to +75°C)
Clock frequency
Clock pulse width
Setup time
Hold time
Delay time
Latch pulse width
EXCK SQCK frequency
EXCK SQCK pulse width
f
CK
t
WCK
t
SU
t
H
t
D
t
WL
f
T
t
WT
750
300
300
300
750
750
0.65
0.65
MHz
ns
ns
ns
ns
ns
MHz
ns
Item
Symbol
Min.
Typ.
Max.
Unit
t
WCK
t
WCK
1/f
CX
t
H
t
SU
t
WL
t
D
1/f
r
t
WT
t
WT
t
H
t
SU
CLK
DATA
XLT
EXCK
CNIN
SQCK
SBSO
SQSO
In low power consumption and special playback mode, when SL0 = SL1 = 1, the maximum operating
frequency for SQCK is 300kHz and the minimum pulse width is 1.5μs.
Description of Functions
1. CPU Interface and Instructions
CPU interface
This interface uses DATA, CLOK, and XLAT to set the modes. The interface timing chart is shown below.
Information on each address and the data is provided in Table 1-1.
The internal registers are initialized by a reset when XRST = 0; the initialization data is shown in Table 1-2.
Note)
When XLAT is low, EXCK and SQCK must be set high.
750ns or more
D1
Data
Address
D2
D3
D0
D1
D2
D3
750ns or more
300ns max
Valid
CLOK
DATA
XLAT
Registers 4 to E
相關(guān)PDF資料
PDF描述
CXD2508AQ CD Digital Signal Processor
CXD2508AR CD Digital Signal Processor
CXD2531BR ATRAC Encoder/Decoder
CXD2545Q CD DIGITAL SIGNAL PROCESSOR WITH BUILT-IN DIGITAL SERV
CXD2550P Digital Filter for CD
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CXD2508AQ 制造商:SONY 制造商全稱:Sony Corporation 功能描述:CD Digital Signal Processor
CXD2508AQ/AR 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CD Digital Signal Processor
CXD2508AR 制造商:SONY 制造商全稱:Sony Corporation 功能描述:CD Digital Signal Processor
CXD2510Q 制造商:SONY 制造商全稱:Sony Corporation 功能描述:CD Digital Signal Processor
CXD2512R 制造商:未知廠家 制造商全稱:未知廠家 功能描述:C-MOS ESP CONTROLLER FOR CD