參數(shù)資料
型號(hào): CXD2585Q
廠商: Sony Corporation
元件分類: 數(shù)字信號(hào)處理
英文描述: CD Digital Signal Processor with Built-in Digital Servo
中文描述: CD數(shù)字信號(hào)處理器的內(nèi)置數(shù)碼舵機(jī)
文件頁數(shù): 6/127頁
文件大?。?/td> 962K
代理商: CXD2585Q
– 6 –
CXD2585Q
Notes)
PCMD is a MSB first, two's complement output.
GTOP is used to monitor the frame sync protection status. (High: sync protection window released.)
XUGF is the frame sync obtained from the EFM signal, and is negative pulse. It is the signal before sync
protection.
XPCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the EFM signal
transition point coincide.
The GFS signal goes high when the frame sync and the insertion protection timing match.
RFCK is derived from the crystal accuracy, and has a cycle of 136μs. (during normal speed)
C2PO represents the data error status.
XROF is generated when the 32K RAM exceeds the ±28F jitter margin.
71
72
73
74
75
76
77
78
79
80
I
O
O
O
O
O
I
I
O
I
1, 0
1, 0
1, 0
1, 0
1, 0
Crystal oscillation circuit input. When the master clock is input externally,
input it from this pin.
Crystal oscillation circuit output.
Serial data output in servo block.
Serial data readout clock output in servo block.
Serial data latch output in servo block.
Sub-Q 80-bit, PCM peak or level data outputs. CD TEXT data output.
SQSO readout clock input.
GRSCOR resynchronization input.
Sub-Q P to W serial output.
SBSO readout clock input.
XTAI
XTAO
SOUT
SOCK
XOLT
SQSO
SQCK
SCSY
SBSO
EXCK
Combination of Monitor Pin Outputs
Command bit
Output data
MTSL1
MTSL0
XUGF
XPCK
GFS
C2PO
MNT0
MNT1
MNT2
MNT3
RFCK
XPCK
XROF
GTOP
0
0
1
0
1
0
Pin
No.
Symbol
I/O
Description
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