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參數(shù)資料
| 型號： | CXD2720Q |
| 廠商： | Sony Corporation |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Single-Chip Digital Signal Processor for Karaoke(卡拉OK單片數(shù)字信號處理器) |
| 中文描述： | 單芯片數(shù)字信號處理器的卡拉OK（卡拉OK單片數(shù)字信號處理器） |
| 文件頁數(shù)： | 13/40頁 |
| 文件大小： | 431K |
| 代理商： | CXD2720Q |
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CXD2720Q
3. Input/Output Synchronization Circuit
[Relevant pins] LRCK, XWO
During normal operation, synchronization is performed automatically to input LRCK (in slave mode), and phase
is matched with serial input data, but if there is a lot of jitter on LRCK, or during power input, synchronization
may be impossible. In this case, forced synchronization can be done by making the XWO pin Low for 2/Fs or
more. Forced synchronization operation is done by the timing of the second LRCK rising edge after the XWO
pin is made Low. When synchronization is completed, return the XWO pin to High.
4. Reset Circuit
[Relevant pins] XRST, XTLI, XTLO
This LSI must be reset after power is turned ON.
Reset is done by making the XRST pin Low for 1/Fs or more after supply voltage satisfies the recommended
operating condition, and the crystal oscillator clock of the XTLI, XTLO pins or the external clock input from the
XTLI pin is correctly applied.
5. Serial Audio Interface (SIF)
[Relevant pins] SI, SO, BCK, LRCK, XS24, XMST
Serial data is used for the external communication of the digital audio data.
The CXD2720Q has one system each for input and output, and each one inputs/outputs 2 channels of data at
1 sampling cycles. Either the 32-bit clock mode or 24-bit clock mode can be selected. In master mode, the 32
bit clock mode is fixed.
(1) Pin Configuration
The pins shown in the table below are assigned to SIF.
Pin
name
SI
SO
BCK
LRCK
XS24
XMST
I
O
I/O
I/O
I
I
Serial input; taken synchronized to BCK.
Serial output; output synchronized to BCK.
BCK input/output; either 32-bit clock mode (64fs) or 24-bit clock mode (48fs). BCK output
supports 32-bit clock mode only.
LRCK input/output (1fs).
SI0 slot number (24/32) selection input. Low: 24-bit slot; High: 32-bit slot. Valid only in slave
mode. Set High in master mode.
BCK, LRCK master mode/slave mode switching input. Low: master mode; High: slave mode.
I/O
Function
Table 5-1. Pin Configuration
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| CXD2721Q-1 | Single-Chip Digital Signal Processor for Karaoke |
| CXD2724AQ-3 | Single-Chip Dolby Pro Logic Surround Decoder(單片杜比環(huán)繞邏輯譯碼器) |
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| CXD2930BR | GPS LSI With Built-In 32-Bit RISC CPU(全球定位系統(tǒng)（GPS）大規(guī)模集成電路(LSI)(內(nèi)置32位RISC中央處理器)) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CXD2720Q-2 | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Single-Chip Dolby Pro Logic Surround Decoder |
| CXD2721Q-1 | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Single-Chip Digital Signal Processor for Karaoke |
| CXD2724AQ-1 | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Single-Chip Dolby Pro Logic Surround Decoder |
| CXD2724AQ-3 | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Single-Chip Dolby Pro Logic Surround Decoder |
| CXD2728Q | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Single-Chip Dolby Pro Logic Surround Decoder |
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