參數(shù)資料
型號: CXD3000R
廠商: Sony Corporation
元件分類: 數(shù)字信號處理
英文描述: CD Digital Signal Processor with Built-in Digital Servo and DAC
中文描述: CD數(shù)字信號處理器,具有內(nèi)置數(shù)字伺服和DAC
文件頁數(shù): 44/129頁
文件大?。?/td> 1264K
代理商: CXD3000R
– 44 –
CXD3000R
I/O sync circuit
Related pins: LRCK and XWO
During normal operation, the I/O sync circuit automatically synchronizes with the input LRCK, and its operation
proceeds in phase with the serial input data. However, there is a chance that synchronization will not be
performed if there is a great deal of jitter in LRCK, or if the power has just been turned on, etc. In this case,
forced synchronization is possible by setting XWO low for 2/Fs or more. Forced synchronization must also be
performed when switching the clock system such as when switching from CLV mode to CAV mode and vice
versa, or when switching the operating frequency, etc. The forced synchronization operation is performed at
the second rising edge of LRCK after the XWO pin is set low.
$BX commands
This command sets the traverse monitor count.
Command
Data 1
Data 2
Data 3
Data 4
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8
2
15
2
14
2
13
2
12
2
11
2
10
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
Traverse monitor count
setting
When the set number of tracks are counted during fine search, the sled control for the traverse cycle control
goes off.
The traverse monitor count is set to monitor the traverse status from the SENS output as COMP and COUT.
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