參數(shù)資料
型號： CXD3000R
廠商： Sony Corporation
元件分類： 數(shù)字信號處理
英文描述： CD Digital Signal Processor with Built-in Digital Servo and DAC
中文描述： CD數(shù)字信號處理器，具有內(nèi)置數(shù)字伺服和DAC
文件頁數(shù)： 85/129頁
文件大?。?/td> 1264K
代理商： CXD3000R
– 85 –
CXD3000R
§4-9. DAC Block Playback Speed
The DAC block playback speed is controlled by sending the DADS command to the DSP block.
Mode
1
2
768fs
384fs
0
1
X'tal
DADS
§4-10. DAC Block Input Timing
The DAC input timing chart is shown below.
Audio data is not transferred from the CD signal processor block to the DAC block inside the CXD3000R. This
is to allow data to be sent to the DAC block via the audio DSP, etc.
When the data is input to the DAC block without using the audio DSP, the data must be connected outside the
LSI. In this case, LRCK, BCK and PCMD can be connected directly with LRCKI, BCKI and PCMDI,
respectively. (See the Application Circuit.)
Normal-Speed Playback
L15
Invalid
L14 L13 L12 L11 L10
L9
L8
L7
L6
L5
L4
L3
L2
L1
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
L0
LRCKI
(44.1k)
BCKI
(2.12M)
PCMDI
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