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參數(shù)資料
| 型號(hào)： | CXD3017Q |
| 廠商： | Sony Corporation |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | CD Digital Signal Processor with Built-in Digital Servo and DAC(CD數(shù)字信號(hào)處理器（內(nèi)置數(shù)字伺服系統(tǒng)和 D/A轉(zhuǎn)換器）) |
| 中文描述： | CD數(shù)字信號(hào)處理器，具有內(nèi)置數(shù)字伺服和DAC（光盤數(shù)字信號(hào)處理器（內(nèi)置數(shù)字伺服系統(tǒng)和的D / A轉(zhuǎn)換器）） |
| 文件頁數(shù)： | 46/117頁 |
| 文件大小： | 778K |
| 代理商： | CXD3017Q |
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CXD3017Q
§2. Subcode Interface
In the CXD3017Q, only SubQ can be readout.
The subcodes P and R to W cannot be readout.
Sub Q can be read out after checking CRC of the 80 bits in the subcode frame.
Sub Q can be read out from the SQSO pin by inputting 80 clock pulses to the SQCK pin when SCOR comes
correctly and CRCF is high.
§2-1. 80-bit Sub Q Readout
Fig. 2-1 shows the peripheral block of the 80-bit Sub Q register.
First, Sub Q, regenerated at one bit per frame, is input to the 80-bit serial/parallel register and the CRC check
circuit.
96-bit Sub Q is input, and if the CRC is OK, it is output to SQSO with CRCF = 1. In addition, 80 bits are
loaded into the parallel/serial register.
When SQSO goes high 400μs (monostable multivibrator time constant) or more after subcode readout, the
CPU determines that the new data (which passed the CRC check) has been loaded.
The CRCF reset is performed by inputting SQCK. When the subcode data is discontinuous after track jump,
etc. CRCF is reset by inputting SQCK. Then, if CRCF =1, the CPU determines that the new data has been
loaded.
When the 80-bit data is loaded, the order of the MSB and LSB is inverted within each byte. As a result,
although the sequence of the bytes is the same, the bits within the bytes are now ordered LSB first.
Once the 80-bit data load is confirmed, SQCK is input so that the data can be read.
The SQCK input is detected, and the retriggerable monostable multivibrator is reset while the input is low.
The retriggerable monostable multivibrator has a time constant from 270 to 400μs. When the duration when
SQCK is high is less than this time constant, the monostable multivibrator is kept reset; during this interval,
the serial/parallel register is not loaded into the parallel/serial register.
While the monostable multivibrator is being reset, data cannot be loaded in the 80-bit parallel/serial register.
In other words, while reading out with a clock cycle shorter than this time constant, the register will not be
rewritten by CRCOK and others. (See Timing Chart 2-2.)
The high and low intervals for SQCK should be between 750ns and 120μs.
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