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參數(shù)資料
| 型號： | CXD3068Q |
| 廠商： | Sony Corporation |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | CD Digital Signal Processor with Built-in Digital Servo(CD數(shù)字信號處理器（內(nèi)置數(shù)字伺服系統(tǒng)）) |
| 中文描述： | CD數(shù)字信號處理器具有內(nèi)置的數(shù)字式伺服（光盤數(shù)字信號處理器（內(nèi)置數(shù)字伺服系統(tǒng)）） |
| 文件頁數(shù)： | 120/135頁 |
| 文件大?。?/td> | 1259K |
| 代理商： | CXD3068Q |
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CXD3068Q
$3E (preset: $3E 00 00)
F1NM, F1DM:
Quasi double accuracy setting for FCS servo filter first-stage
On when 1; default when 0.
F1NM: Gain normal
F1DM: Gain down
Quasi double accuracy setting for TRK servo filter first-stage
On when 1; default when 0.
T1NM: Gain normal
T1UM: Gain up
Quasi double accuracy setting for FCS servo filter third-stage
On when 1; default when 0.
Generally, the advance amount of the phase becomes large by partially setting the FCS servo
third-stage filter which is used as the phase compensation filter to double accuracy.
F3NM: Gain normal
F3DM: Gain down
Quasi double accuracy setting for TRK servo filter third-stage
On when 1; default when 0.
Generally, the advance amount of the phase becomes large by partially setting the TRK servo
third-stage filter which is used as the phase compensation filter to double accuracy.
T3NM: Gain normal
T3UM: Gain up
T1NM, T1UM:
F3NM, F3DM:
T3NM, T3UM:
Note)
Filter first- and third-stage quasi double accuracy settings can be set individually.
See "§ 5-20 Filter Composition" at the end of this specification concerning quasi double accuracy.
DFIS:
FCS hold filter input extraction node selection
0: M05 (Data RAM address 05); default
1: M04 (Data RAM address 04)
This command masks the TLC2 command set by D2 of $38 only when FOK is low.
On when 1; default when 0
When 0, the internally generated LOCK signal is output to the LOCK pin. (default)
When 1, the LOCK signal can be input from an external source to the LOCK pin.
When 0, the internally generated COUT signal is output to the COUT pin. (default)
When 1, the COUT signal can be input from an external source to the COUT pin.
TLCD:
LKIN:
COIN:
The MIRR, DFCT and FOK signals can also be input from an external source.
MDFI:
When 0, the MIRR, DFCT and FOK signals are generated internally. (default)
When 1, the MIRR, DFCT and FOK signals can be input from an external source through the
MIRR, DFCT and FOK pins.
MIRI:
When 0, the MIRR signal is generated internally. (default)
When 1, the MIRR signal can be input from an external source through the MIRR pin.
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
F1NM F1DM F3NM F3DM
T1NM T1UM T3NM T3UM
DFIS TLCD
0
LKIN COIN MDFI MIRI XT1D
XT1D:
When XT1D = 1, the input to the servo master clock can be used without dividing its
frequency. This command takes precedence over the XTSL pin, XT2D and XT4D. See the
description of $3F for XT2D and XT4D.
MDFI
0
0
1
0
1
—
MIRR, DFCT and FOK are all generated internally.
MIRR only is input from an external source.
MIRR, DFCT and FOK are all input from an external source.
MIRI
: preset, —: don't care
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