參數(shù)資料
型號(hào)： CXD4017R
廠商： Sony Corporation
元件分類： 數(shù)字信號(hào)處理
英文描述： Reception Digital Signal Processor IC for Infrared Spatial Digital Audio Communication
中文描述： 接待數(shù)字信號(hào)處理器芯片的紅外空間數(shù)字音頻通信
文件頁(yè)數(shù)： 15/34頁(yè)
文件大小： 1102K
代理商： CXD4017R
– 15 –
CXD4017R
5. Description of audio DAC interface
(1) In this LSI, the audio DAC can be directly coupled. If the on-chip PLL circuit is used, a 256fs clock pulse is
output to the APX pin.
DAOUT:
DAC data
BCK:
DAC bit clock pulse
LRCK:
DAC sample clock pulse
DTVALID: Data valid flag (low: invalid, high: valid)
(2) The emphasis and sampling frequency information is output to the EMPFS0 pin and EMPFS1 pin.
(3) The data valid flag DTVALID indicates the valid_flag contained in the Source_Info and the errors in
communication. When this pin is low, it indicates that the valid_flag is "0" or that some kind of error,
including any errors in the input signals at the transmission end, has occurred at some point after these
signals were input.
(4) Sixty-four BCK cycles are contained in one LRCK cycle.
(5) The DAOUT output format can be changed by the DIFM register (3 bits) with address 00h when SCMODE
is high (serial setting mode) and by the DIFM1 pin and DIFM0 pin when SCMODE is low (pin setting
mode).
EMPFS1
Low
Low
High
High
Emphasis
Not provided
Provided
Provided
Provided
Sampling frequency
No information
44.1kHz
48kHz
32kHz
EMPFS0
Low
High
Low
High
Output mode
Mode-0
Mode-1
Mode-2
Mode-3
Mode-4
Mode-5
Mode-6
Mode-7
SCMODE = High
SCMODE = Low
DIFM1
Low
Low
High
High
DIFM0
Low
High
Low
High
DIFM
000
001
010
011
100
101
110
111
No settings possible
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