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參數(shù)資料
| 型號(hào)： | CXD8302Q |
| 廠商： | Sony Corporation |
| 英文描述： | PLL For CCD Cameras(用于CCD照相機(jī)的鎖相環(huán)電路) |
| 中文描述： | CCD相機(jī)的PLL（用于防治荒漠化公約照相機(jī)的鎖相環(huán)電路） |
| 文件頁(yè)數(shù)： | 1/10頁(yè) |
| 文件大?。?/td> | 183K |
| 代理商： | CXD8302Q |
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CXD8302Q
E94320A52-PP
PLL for CCD Cameras
For the availability of this product, please contact the sales office.
Description
The CXD8302Q has the functions needs to
configure a PLL circuit with a timing generator and
external sync signals for a CCD of 480K pixels (EIA,
effective pixels) and 570K pixels (CCIR, effective
pixels).
Features
EIA and CCIR compatible
Compatible with component digital and composite
digital recording format
Both SYNC and VD/HD signals can be used for
external sync signals
Absolute Maximum Ratings
Supply voltage
Input voltage
Storage temperature Tstg
V
DD
V
I
V
SS
– 0.3 to +7
V
SS
– 0.3 to V
DD
+0.3
–40 to +125
V
V
°C
Recommended Operating Conditions
Supply voltage
Operating temperature
Topr
V
DD
4.5 to 5.5
0 to 70
V
°C
Block Diagram
Applications
CCD cameras
Structure
Silicon gate CMOS IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
44 pin QFP (Plastic)
2f
H
V reset
8
f
H
f
V
Separation
of f
H
and f
V
Frequency Division
EIA : 1/525
CCIR: 1/625
L
65 Clocks
Delay
INTf
H
HD
VD
SYNC
BLK
EXTSYNC
EXTHD
MODE1
EIA/CCIR
CLKI
CLKO
EXTf
H
EXTVD
INTf
H
phase setting
V latch
MODE2
H timing
V timing
Frequency Division
EIA : 1/572
(1/568)
CCIR: 1/576
(1/567)
15
14
13
26
31
32
38
2
3
4
7
8
9 10 11
37
44
43
42
41
20
19
P
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