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– 23 –
CXP84716/84720/84724
Serial transfer (CH2)
(Ta = –20 to +75°C, V
DD
= 4.5 to 5.5V, Vss = 0V reference)
Item
Symbol
Pin
Min.
Max.
Unit
Conditions
SCK cycle time
SCK High and Low
level widths
SI input setup time
(for SCK
↑
)
SI input hold time
(for SCK
↑
)
SCK
↓ →
SO delay time
t
KCY
t
KH
t
KL
t
SIK
t
KSI
t
KSO
SCK2
SCK2
SI2
SI2
SO2
Input mode
Output mode
Input mode
Output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
1000
8000/fc
400
4000/fc – 50
100
200
200
100
200
100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 1)
t
sys indicates three values according to the contents of the clock control register (CLC: 00FE
h
) upper 2
bits (CPU clock selection).
t
sys [ns] = 2000/fc (Upper 2 bits = “00”), 4000/fc (Upper 2 bits = “01’), 16000/fc (Upper 2 bits = “11”)
Note 2)
SCK, SI and SO represent SCK2, SI2 and SO2 for CH2, respectively.
Note 3)
The load of SCK2 output mode and SO2 output delay time is 50pF+1TTL.
Serial transfer (CH2)
(Ta = –20 to +75°C, V
DD
= 3.0 to 3.6V, Vss = 0V reference)
Note 1)
t
sys indicates three values according to the contents of the clock control register (CLC: 00FE
h
) upper 2
bits (CPU clock selection).
t
sys [ns] = 2000/fc (Upper 2 bits = “00”), 4000/fc (Upper 2 bits = “01’), 16000/fc (Upper 2 bits = “11”)
Note 2)
SCK, SI and SO represent SCK2, SI2 and SO2 for CH2, respectively.
Note 3)
The load of SCK2 output mode and SO2 output delay time is 50pF.
Item
Symbol
Pin
Min.
Max.
Unit
Conditions
SCK cycle time
SCK High and Low
level widths
SI input setup time
(for SCK
↑
)
SI input hold time
(for SCK
↑
)
SCK
↓ →
SO delay time
t
KCY
t
KH
t
KL
t
SIK
t
KSI
t
KSO
SCK2
SCK2
SI2
SI2
SO2
Input mode
Output mode
Input mode
Output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
1000
8000/fc
400
4000/fc – 100
100
200
200
100
250
125
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns