- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄295352 > CY14E102N-ZSP45XIT (CYPRESS SEMICONDUCTOR CORP) 128K X 16 NON-VOLATILE SRAM, 45 ns, PDSO54 PDF資料下載
參數(shù)資料
| 型號(hào)： | CY14E102N-ZSP45XIT |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 128K X 16 NON-VOLATILE SRAM, 45 ns, PDSO54 |
| 封裝： | ROHS COMPLIANT, TSOP2-54 |
| 文件頁(yè)數(shù)： | 17/21頁(yè) |
| 文件大?。?/td> | 628K |
| 代理商： | CY14E102N-ZSP45XIT |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)當(dāng)前第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)
ADVANCE
CY14E102L, CY14E102N
Document Number: 001-45755 Rev. *A
Page 5 of 21
Hardware RECALL (Power Up)
During
power
up
or
after
any
low
power
condition
(VCC<VSWITCH), an internal RECALL request is latched. When
VCC again exceeds the sense voltage of VSWITCH, a RECALL
cycle is automatically initiated and takes tHRECALL to complete.
Software STORE
Transfer data from the SRAM to the nonvolatile memory with a
software address sequence. The CY14E102L/CY14E102N
software STORE cycle is initiated by executing sequential
CE-controlled READ cycles from six specific address locations
in exact order. During the STORE cycle an erase of the previous
nonvolatile data is first performed, followed by a program of the
nonvolatile elements. After a STORE cycle is initiated, further
input and output are disabled until the cycle is completed.
Because a sequence of READs from specific addresses is used
for STORE initiation, it is important that no other READ or WRITE
accesses intervene in the sequence. If there are intervening
READ or WRITE accesses, the sequence is aborted and no
STORE or RECALL takes place.
To initiate the software STORE cycle, the following READ
sequence must be performed.
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x8FC0 Initiate STORE Cycle
The software sequence may be clocked with CE controlled
READs or OE controlled READs. After the sixth address in the
sequence is entered, the STORE cycle commences and the chip
is disabled. It is important to use READ cycles and not WRITE
cycles in the sequence, although it is not necessary that OE be
LOW for a valid sequence. After the tSTORE cycle time is fulfilled,
the SRAM is activated again for the READ and WRITE operation.
Software RECALL
Transfer the data from the nonvolatile memory to the SRAM with
a software address sequence. A software RECALL cycle is
initiated with a sequence of READ operations in a manner similar
to the software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE controlled READ operations must
be performed:
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x4C63 Initiate RECALL Cycle
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared and then, the nonvolatile information is transferred into
the SRAM cells. After the tRECALL cycle time, the SRAM is again
ready for READ and WRITE operations. The RECALL operation
does not alter the data in the nonvolatile elements.
Table 1. Mode Selection
CE
WE
OE
A15 - A0
Mode
IO
Power
H
X
Not Selected
Output High Z
Standby
L
H
L
X
Read SRAM
Output Data
Active
L
X
Write SRAM
Input Data
Active
L
H
L
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8B45
Read SRAM
AutoStore
Disable
Output Data
Active[5,6,7]
L
H
L
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4B46
Read SRAM
AutoStore Enable
Output Data
Active[5,6,7]
Notes
5. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle.
6. While there are 18/17 address lines on the CY14E102L/CY14E102N, only the lower 16 lines are used to control software modes.
7. IO state depends on the state of OE, BHE, and BLE. The IO table shown assumes OE, BHE, and BLE LOW.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY21DF-FREQ2-OUT23 | VCXO, CLOCK, 65 MHz - 160 MHz, CMOS/TTL OUTPUT |
| CY23CH-FREQ-OUT23 | VCXO, CLOCK, 1.25 MHz - 65 MHz, CMOS/TTL OUTPUT |
| CY22DF-FREQ2-OUT23 | VCXO, CLOCK, 65 MHz - 160 MHz, CMOS/TTL OUTPUT |
| CY12FF-FREQ1-OUT23 | VCXO, CLOCK, 1.25 MHz - 65 MHz, CMOS/TTL OUTPUT |
| CY33AF-FREQ2-OUT23 | VCXO, CLOCK, 65 MHz - 160 MHz, CMOS/TTL OUTPUT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY14E108L-BA45XCES | 制造商:Cypress Semiconductor 功能描述:NVSRAM 8MB 1024KX8 FBGA COMMERCIAL TEMP - Trays |
| CY14E108N-BA45XCES | 制造商:Cypress Semiconductor 功能描述:NVSRAM 8MB 512KX16 5 VOLT FBGA COMMERCIAL TEMP - Trays |
| CY14E256LA-SZ25XI | 功能描述:NVRAM 32Kb x8 4.5-5.5V NVSRAM RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲(chǔ)容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問時(shí)間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
| CY14E256LA-SZ25XIT | 功能描述:NVRAM 32Kb x8 4.5-5.5V NVSRAM RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲(chǔ)容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問時(shí)間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
| CY14E256LA-SZ45XI | 功能描述:NVRAM 32Kb x8 4.5-5.5V NVSRAM RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲(chǔ)容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問時(shí)間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。