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參數(shù)資料
| 型號(hào)： | CY2308ZC-1H |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 3.3V Zero Delay Buffer |
| 中文描述： | 2308 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 封裝： | 4.40 MM, MO-153, TSSOP-16 |
| 文件頁數(shù)： | 7/14頁 |
| 文件大?。?/td> | 203K |
| 代理商： | CY2308ZC-1H |
CY2308
Document #: 38-07146 Rev. *C
Page 2 of 14
Notes:
1. Weak pull-down.
2. Weak pull-down on all outputs.
3. Weak pull-ups on these inputs.
4. Outputs inverted on 2308–2 and 2308–3 in bypass mode, S2 = 1 and S1 = 0.
5. Output phase is indeterminant (0° or 180° from input clock). If phase integrity is required, use the CY2308–2.
Pin Description
Pin
Signal
Description
1REF[1]
Input reference frequency, 5V tolerant input
2
CLKA1[2]
Clock output, Bank A
3
CLKA2[2]
Clock output, Bank A
4VDD
3.3V supply
5
GND
Ground
6
CLKB1[2]
Clock output, Bank B
7
CLKB2[2]
Clock output, Bank B
8S2[3]
Select input, bit 2
9S1[3]
Select input, bit 1
10
CLKB3[2]
Clock output, Bank B
11
CLKB4[2]
Clock output, Bank B
12
GND
Ground
13
VDD
3.3V supply
14
CLKA3[2]
Clock output, Bank A
15
CLKA4[2]
Clock output, Bank A
16
FBK
PLL feedback input
Select Input Decoding
S2
S1
CLOCK A1–A4
CLOCK B1–B4
Output Source
PLL Shutdown
0
Three-State
PLL
Y
0
1
Driven
Three-State
PLL
N
10
Driven[4]
Reference
Y
1
Driven
PLL
N
Available CY2308 Configurations
Device
Feedback From
Bank A Frequency
Bank B Frequency
CY2308–1
Bank A or Bank B
Reference
CY2308–1H
Bank A or Bank B
Reference
CY2308–2
Bank A
Reference
Reference/2
CY2308–2
Bank B
2 X Reference
Reference
CY2308–3
Bank A
2 X Reference
Reference or Reference[5]
CY2308–3
Bank B
4 X Reference
2 X Reference
CY2308–4
Bank A or Bank B
2 X Reference
CY2308–5H
Bank A or Bank B
Reference /2
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY2308ZC-5H | 3.3V Zero Delay Buffer |
| CY2308ZI-1H | 3.3V Zero Delay Buffer |
| CY2308ZI-5H | 3.3V Zero Delay Buffer |
| CY2308ZXI-1H | 3.3V Zero Delay Buffer |
| CY2308ZXI-5H | 3.3V Zero Delay Buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY2308ZC-1HT | 制造商:Cypress Semiconductor 功能描述:Zero Delay PLL Clock Driver Single 10MHz to 133MHz 16-Pin TSSOP T/R |
| CY2308ZC-5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Eight Distributed-Output Clock Driver |
| CY2308ZC-5H | 功能描述:IC CLK ZDB 8OUT 133MHZ 16TSSOP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標(biāo)準(zhǔn)包裝:96 系列:- 類型:時(shí)鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
| CY2308ZC-5HT | 制造商:Cypress Semiconductor 功能描述:Zero Delay PLL Clock Driver Single 10MHz to 133MHz 16-Pin TSSOP T/R |
| CY2308ZI1H | 制造商:CYPRESS 功能描述:New |
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