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參數(shù)資料
| 型號(hào)： | CY23FP12OXCT |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | Coaxial Cable; Coaxial RG/U Type:58A; Impedance:52ohm; Conductor Size AWG:20; No. Strands x Strand Size:19 x 32; Jacket Material:Polyvinylchloride (PVC); Leaded Process Compatible:Yes; Voltage Nom.:300V RoHS Compliant: Yes |
| 中文描述： | 23FP SERIES, PLL BASED CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 封裝： | 5.30 MM, LEAD FREE, SSOP-28 |
| 文件頁(yè)數(shù)： | 4/10頁(yè) |
| 文件大?。?/td> | 201K |
| 代理商： | CY23FP12OXCT |
CY23FP12
Document #: 38-07246 Rev. *E
Page 4 of 10
Below is a list of independent functions, which can be
assigned to each of the four S1 and S2 combinations. When
a particular S1 and S2 combination is selected, the device will
assume the configuration (which is essentially a set of
functions given in
Table 2
, below) that has been preassigned
to that particular combination.
Inv CLKB4
Generates an inverted clock on the CLKB4 output. When this option is
programmed, CLKB4 and CLKB5 will become complimentary pairs.
Enables/Disables internal pulldowns on all outputs
Enables/Disables internal pulldowns on the feedback path (applicable to both
internal and external feedback topologies)
Selects between the internal and the external feedback topologies
Non-invert
Pull-down Enable
Fbk Pull-down Enable
Enable
Enable
Fbk Sel
External
Table 1.
(continued)
Configuration
Description
Default
Table 2.
Function
Description
Default
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Output Enable CLKB[5:4] Enables/Disables CLKB[5:4] output pair
Output Enable CLKB[3:2] Enables/Disables CLKB[3:2] output pair
Output Enable CLKB[1:0] Enables/Disables CLKB[1:0] output pair
Output Enable CLKA[5:4] Enables/Disables CLKA[5:4] output pair
Output Enable CLKA[3:2] Enables/Disables CLKA[3:2] output pair
Output Enable CLKA[1:0] Enables/Disables CLKA[1:0] output pair
Auto Power-down Enable Enables/Disables the auto power down circuit, which monitors the reference clock rising
edges and shuts down the device in case of a reference “failure.” This failure is triggered
by a drift in reference frequency below a set limit. This auto power down circuit is
disabled internally when one or more of the outputs are configured to be driven directly
from the reference clock.
PLL Power-down
Shuts down the PLL when the device is configured as a non-PLL fanout buffer.
M[7:0]
Assigns an eight-bit value to reference divider –M. The divider can be any integer value
from 1 to 256; however, the PLL input frequency cannot be lower than 10 MHz.
N[7:0]
Assigns an eight-bit value to feedback divider –N. The divider can be any integer value
from 1 to 256; however, the PLL input frequency cannot be lower than 10 MHz.
X[6:0]
Assigns a seven-bit value to output divider –X. The divider can be any integer value
from 5 to 130. Divide by 1,2,3, and 4 are preprogrammed on the device and can be
activated by the appropriate output mux setting.
Divider Source
Selects between the PLL output and the reference clock as the source clock for the
output dividers.
CLKA54 Source
Independently selects one out of the eight possible output dividers that will connect to
the CLKA5 and CLKA4 pair. Please refer to
Table 3
for a list of divider values.
CLKA32 Source
Independently selects one out of the eight possible output dividers that will connect to
the CLKA3 and CLKA2 pair. Please refer to
Table 3
for a list of divider values.
CLKA10 Source
Independently selects one out of the eight possible output dividers that will connect to
the CLKA1 and CLKA0 pair. Please refer to
Table 3
for a list of divider values.
CLKB54 Source
Independently selects one out of the eight possible output dividers that will connect to
the CLKB5 and CLKB4 pair. Please refer to
Table 3
for a list of divider values.
CLKB32 Source
Independently selects one out of the eight possible output dividers that will connect to
the CLKB3 and CLKB2 pair. Please refer to
Table 3
for a list of divider values.
CLKB10 Source
Independently selects one out of the eight possible output dividers that will connect to
the CLKB1 and CLKB0 pair. Please refer to
Table 3
for a list of divider values.
PLL Enabled
2
2
1
PLL
Divide by 2
Divide by 2
Divide by 2
Divide by 2
Divide by 2
Divide by 2
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| CY23FP12OXI | Multiconductor Cable; Number of Conductors:2; Conductor Size AWG:16; No. Strands x Strand Size:19 x 29; Jacket Material:Polyvinylchloride (PVC); Number of Pairs:1; Leaded Process Compatible:Yes; Temperature Max:105 C RoHS Compliant: Yes |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY23FP12OXI | 功能描述:鎖相環(huán) - PLL 3.3V 200MHz IND RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CY23FP12OXIT | 功能描述:鎖相環(huán) - PLL 3.3V 200MHz IND RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CY23FS04 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Failsafe⑩ 2.5V/ 3.3V Zero Delay Buffer |
| CY23FS04_05 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Failsafe⑩ 2.5V/ 3.3V Zero Delay Buffer |
| CY23FS04KZXI | 制造商:Cypress Semiconductor 功能描述: |
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