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參數(shù)資料
| 型號： | CY3692 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | SCREWDRIVER, XONIC SLOT 3 X 100SCREWDRIVER, XONIC SLOT 3 X 100; Tip Size A x B:3 x 0.5mm; Tip size:3mm; Length, blade:100mm; Length, Inches:4"; Handle type:SHATTERPROOF CELLULOSE ACETATE; Tip Size:3 mm; Tip type:Parallel Slot |
| 中文描述： | 200 - MHz的現(xiàn)場可編程零延遲緩沖器 |
| 文件頁數(shù)： | 1/10頁 |
| 文件大?。?/td> | 201K |
| 代理商： | CY3692 |
200-MHz Field Programmable Zero Delay Buffer
CY23FP12
Cypress Semiconductor Corporation
Document #: 38-07246 Rev. *E
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised December 13, 2004
Features
Fully field-programmable
— Input and output dividers
— Inverting/noninverting outputs
— Phase-locked loop (PLL) or fanout buffer configu-
ration
10-MHz to 200-MHz operating range
Split 2.5V or 3.3V outputs
Two LVCMOS reference inputs
Twelve low-skew outputs
—
35ps typ. output-to-output skew (same freq)
110 ps typ. cycle-cycle jitter (same freq)
Three-stateable outputs
< 50-
μ
A shutdown current
Spread Aware
28-pin SSOP
3.3V operation
Industrial temperature available
Functional Description
The CY23FP12 is a high-performance fully field-program-
mable 200 MHz zero delay buffer designed for high speed
clock distribution. The integrated PLL is designed for low jitter
and optimized for noise rejection. These parameters are
critical for reference clock distribution in systems using
high-performance ASICs and microprocessors.
The CY23FP12 is fully programmable via volume or prototype
programmers enabling the user to define an appli-
cation-specific Zero Delay Buffer with customized input and
output dividers, feedback topology (internal/external), output
inversions, and output drive strengths. For additional flexibility,
the user can mix and match multiple functions, listed in
Table 2
, and assign a particular function set to any one of the
four possible S1-S2 control bit combinations. This feature
allows for the implementation of four distinct personalities,
selectable with S1-S2 bits, on a single programmed silicon.
The CY23FP12 also features a proprietary auto-power-down
circuit that shuts down the device in case of a REF failure,
resulting in less than 50
μ
A of current draw.
The CY23FP12 provides twelve outputs grouped in two banks
with separate power supply pins which can be connected
independently to either a 2.5V or a 3.3V rail.
Selectable reference input is a fault tolerance feature which
allows for glitch-free switch over to secondary clock source
when REFSEL is asserted/deasserted.
21
28
REFSEL
FBK
CLKA0
CLKA1
V
SSA
CLKA2
CLKA3
V
DDA
V
SSA
CLKA4
CLKA5
1
2
3
4
5
6
7
8
22
23
24
25
26
27
REF2
REF1
CLKB0
CLKB1
V
SSB
CLKB2
CLKB3
V
DDB
V
SSB
CLKB4
CLKB5
SSOP
Top View
Pin Configuration
17
V
DDA
V
SSC
S1
20
19
18
16
15
9
12
V
DDB
V
DDC
S2
13
10
11
14
VDDC
FBK
÷
M
÷
N
100 to
400MHz
PLL
CLKA1
CLKA3
CLKA2
REF2
REFSEL
CLKA4
CLKA5
VSSA
VDDB
CLKB1
CLKB3
CLKB2
CLKB4
CLKB5
VSSB
VDDA
÷
2
÷
3
÷
4
÷
X
CLKA0
VSSC
÷
1
Lock Detect
Test Logic
REF1
CLKB0
S[2:1]
Function
Selection
Block Diagram
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