參數(shù)資料
型號(hào)： CY23FP12OXI
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： 時(shí)鐘及定時(shí)
英文描述： Multiconductor Cable; Number of Conductors:2; Conductor Size AWG:16; No. Strands x Strand Size:19 x 29; Jacket Material:Polyvinylchloride (PVC); Number of Pairs:1; Leaded Process Compatible:Yes; Temperature Max:105 C RoHS Compliant: Yes
中文描述： 23FP SERIES, PLL BASED CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28
封裝： 5.30 MM, LEAD FREE, SSOP-28
文件頁(yè)數(shù)： 3/10頁(yè)
文件大?。?/td> 201K
代理商： CY23FP12OXI
CY23FP12
Document #: 38-07246 Rev. *E
Page 3 of 10
Below is a list of independent functions that can be
programmed with a volume or prototype programmer on the
“default” silicon.
/1,/2,/3,/4,
/x,/2x
/1,/2,/3,/4,
/x,/2x
/1,/2,/3,/4,
/x,/2x
/1,/2,/3,/4,
/x,/2x
/1,/2,/3,/4,
/x,/2x
/1,/2,/3,/4,
/x,/2x
PLL
/M
/N
Output
Function
Select
Matrix
REF
FBK
CLKB5
CLKB4
CLKB3
CLKB2
CLKB1
CLKB0
CLKA5
CLKA4
CLKA3
CLKA2
CLKA1
CLKA0
Figure 1. Basic PLL Block Diagram
Table 1.
Configuration
Description
Default
+16 mA
DC Drive Bank A
Programs the drive strength of Bank A outputs. The user can select one out
of two possible drive strength settings that produce output DC currents in the
range of ±16 mA to ±20 mA.
Programs the drive strength of Bank B outputs. The user can select one out
of two possible drive strength settings that produce output DC currents in the
range of ±16 mA to ±20 mA.
Enables/Disables CLKB[5:0] outputs. Each of the six outputs can be disabled
individually
if not used, to minimize electromagnetic interference (EMI) and
switching noise.
Enables/Disables CLKA[5:0] outputs. Each of the six outputs can be disabled
individually
if not used, to minimize EMI and switching noise.
Generates an inverted clock on the CLKA0 output. When this option is
programmed, CLKA0 and CLKA1 will become complimentary pairs.
Generates an inverted clock on the CLKA2 output. When this option is
programmed, CLKA2 and CLKA3 will become complimentary pairs.
Generates an inverted clock on the CLKA4 output. When this option is
programmed, CLKA4 and CLKA5 will become complimentary pairs.
Generates an inverted clock on the CLKB0 output. When this option is
programmed, CLKB0 and CLKB1 will become complimentary pairs.
Generates an inverted clock on the CLKB2 output. When this option is
programmed, CLKB2 and CLKB3 will become complimentary pairs.
DC Drive Bank B
+16 mA
Output Enable for Bank B clocks
Enable
Output Enable for Bank A clocks
Enable
Inv CLKA0
Non-invert
Inv CLKA2
Non-invert
Inv CLKA4
Non-invert
Inv CLKB0
Non-invert
Inv CLKB2
Non-invert
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY23FP12OXIT 功能描述:鎖相環(huán) - PLL 3.3V 200MHz IND RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
CY23FS04 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Failsafe⑩ 2.5V/ 3.3V Zero Delay Buffer
CY23FS04_05 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Failsafe⑩ 2.5V/ 3.3V Zero Delay Buffer
CY23FS04KZXI 制造商:Cypress Semiconductor 功能描述:
CY23FS04ZC 制造商:Rochester Electronics LLC 功能描述:FAILSAFE 2.5V/3.3V ZERO DELAY BUFFER TSSOP16 - Bulk 制造商:Cypress Semiconductor 功能描述:
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