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參數(shù)資料
| 型號： | CY28317PVXC-2T |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 2/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK FTG VIA PL/E133T 48SSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 時(shí)鐘/頻率發(fā)生器 |
| PLL： | 是 |
| 輸入： | 晶體 |
| 輸出： | HCSL，LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:20 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 248MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-BSSOP（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 48-SSOP |
| 包裝： | 帶卷 (TR) |
CY28317-2
..................... Document #: 38-07094 Rev. *B Page 10 of 20
Byte 11: Recovery Frequency N-Value Register
Bit
Name
Default
Pin Description
Bit 7
ROCV_FREQ_N7
0
If ROCV_FREQ_SEL is set, CY28317-2 will use the values programmed in
ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] to determine the recovery
CPU output frequency when a Watchdog Timer time-out occurs.
The setting of the FS_Override bit determines the frequency ratio for CPU and
PCI. When it is cleared, CY28317-2 will use the same frequency ratio stated
in the Latched FS[4:0] register. When it is set, CY28317-2 will use the
frequency ratio stated in the SEL[4:0] register.
CY28317-2 supports programmable CPU frequencies ranging from 50 MHz to
248 MHz.
CY28317-2 will change the output frequency whenever there is an update to
either ROCV_FREQ_N[7:0] or ROCV_FREQ_M[6:0]. Therefore, it is recom-
mended to use word or block Write to update both registers within the same
SMBus bus operation.
Bit 6
ROCV_FREQ_N6
0
Bit 5
ROCV_FREQ_N5
0
Bit 4
ROCV_FREQ_N4
0
Bit 3
ROCV_FREQ_N3
0
Bit 2
ROCV_FREQ_N2
0
Bit 1
ROCV_FREQ_N1
0
Bit 0
ROCV_FREQ_N0
0
Byte 12: Recovery Frequency M-Value Register
Bit
Name
Default
Pin Description
Bit 7
ROCV_FREQ_SEL
0
ROCV_FREQ_SEL determines the source of the recover frequency when a
Watchdog Timer time-out occurs. The clock generator will automatically switch
to the recovery CPU frequency based on the selection on ROCV_FREQ_SEL.
0 = From latched FS[4:0]
1 = From the settings of ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0]
Bit 6
ROCV_FREQ_M6
0
If ROCV_FREQ_SEL is set, CY28317-2 will use the values programmed in
ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] to determine the recovery
CPU output frequency when a Watchdog Timer time-out occurs.
The setting of the FS_Override bit determines the frequency ratio for CPU,
SDRAM, and PCI. When it is cleared, CY28317-2 will use the same frequency
ratio stated in the Latched FS[4:0] register. When it is set, CY28317-2 will use
the frequency ratio stated in the SEL[4:0] register.
CY28317-2 supports programmable CPU frequencies ranging from 50 MHz to
248 MHz.
CY28317-2 will change the output frequency whenever there is an update to
either ROCV_FREQ_N[7:0] or ROCV_FREQ_M[6:0]. Therefore, it is recom-
mended to use word or block Write to update both registers within the same
SMBus bus operation.
Bit 5
ROCV_FREQ_M5
0
Bit 4
ROCV_FREQ_M4
0
Bit 3
ROCV_FREQ_M3
0
Bit 2
ROCV_FREQ_M2
0
Bit 1
ROCV_FREQ_M1
0
Bit 0
ROCV_FREQ_M0
0
Byte 13: Programmable Frequency Select N-Value Register
Bit
Name
Default
Pin Description
Bit 7
CPU_FSEL_N7
0
If Prog_Freq_EN is set, CY28317-2 will use the values programmed in
CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] to determine the CPU output
frequency. The new frequency will start to load whenever CPU_FSELM[6:0]
is updated.
The setting of the FS_Override bit determines the frequency ratio for CPU,
SDRAM and PCI. When it is cleared, CY28317-2 will use the same frequency
ratio stated in the Latched FS[4:0] register. When it is set, CY28317-2 will use
the frequency ratio stated in the SEL[4:0] register.
CY28317-2 supports programmable CPU frequencies ranging from 50 MHz
to 248 MHz.
Bit 6
CPU_FSEL_N6
0
Bit 5
CPU_FSEL_N5
0
Bit 4
CPU_FSEL_N4
0
Bit 3
CPU_FSEL_N3
0
Bit 2
CPU_FSEL_N2
0
Bit 1
CPU_FSEL_N1
0
Bit 0
CPU_FSEL_N0
0
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