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參數(shù)資料
| 型號： | CY28317PVXC-2T |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 8/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK FTG VIA PL/E133T 48SSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 時(shí)鐘/頻率發(fā)生器 |
| PLL： | 是 |
| 輸入： | 晶體 |
| 輸出： | HCSL，LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:20 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 248MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-BSSOP（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 48-SSOP |
| 包裝： | 帶卷 (TR) |
CY28317-2
..................... Document #: 38-07094 Rev. *B Page 16 of 20
AC Electrical Characteristics
TA = 0°C to +70°C, VDDQ3 = 3.3V±5%, fXTL = 14.31818 MHz
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the
clock output; Spread Spectrum is disabled.
Notes:
5. X1 input threshold voltage (typical) is VDD/2.
6. The CY28317-2 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. The total load placed on the
crystal is 18 pF; this includes typical stray capacitance of short PCB traces to the crystal.
7. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).
8. Determined as a fraction of 2* (tRP – tRN). Where tRP is a rising edge and tRN is an intersection falling edge.
Crystal Oscillator
VTH
X1 Input Threshold Voltage[5]
VDDQ3 = 3.3V
1.65
V
CLOAD
Load Capacitance, Imposed on
External Crystal[6]
18
pF
CIN,X1
X1 Input Capacitance[7]
Pin X2 unconnected
TBD
pF
Pin Capacitance/Inductance
CIN
Input Pin Capacitance
Except X1 and X2
5
pF
COUT
Output Pin Capacitance
6
pF
LIN
Input Pin Inductance
7nH
DC Electrical Characteristics: TA = 0°C to +70°C, VDDQ3 = 3.3V ±5%
[3] (continued)
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
CPU Clock Outputs[8]
Parameter
Description
Test Condition/Comments
CPU = 100 MHz
CPU = 133 MHz
Unit
Min.
Typ.
Max.
Min.
Typ.
Max.
tR
Output Rise Edge Rate
1.0
4.0
1.0
4.0
v/ns
tF
Output Fall Edge Rate
1.0
2.0
1.0
2.0
v/ns
tD
Duty Cycle
Measured at 50% point
45
55
45
55
%
tJC
Jitter, Cycle to Cycle
250
ps
fST
Frequency Stabilization
from Power-up (cold
start)
Assumes full supply voltage reached
within 1 ms from power-up. Short
cycles exist prior to frequency
stabilization.
33
ms
Zo
AC Output Impedance
VO = VX
50
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