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參數(shù)資料
| 型號： | CY28442ZXC-2T |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 18/19頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK ALVISO PENTM 56TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 類型： | 時鐘/頻率發(fā)生器 |
| PLL： | 是 |
| 主要目的： | Intel CPU 服務(wù)器 |
| 輸入： | LVTTL，晶體 |
| 輸出： | HCSL，LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 3:20 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 200MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-TFSOP（0.240"，6.10mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 56-TSSOP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | SLCY28442ZXC-2T |
CY28442-2
....................... Document #: 38-07691 Rev. *B Page 8 of 19
1
0
CLKREQ#A
SRC[T/C]2 CLKREQ#A control
1 = SRC[T/C]2 stoppable by CLKREQ#A pin
0 = SRC[T/C]2 not controlled by CLKREQ#A pin
0
RESERVED
Byte 9: Control Register 9
Bit
@Pup
Name
Description
7
0
S3
96_100_SSC Spread Spectrum Selection table:
S[3:0]
SS%
‘0000’ = –0.8%(Default value)
‘0001’ = –1.0%
‘0010’ = –1.25%
‘0011’ = –1.5%
‘0100’ = –1.75%
‘0101’ = –2.0%
‘0110’ = –2.5%
‘0111’ = –0.5%
‘1000’ = ±0.25%
‘1001’ = ±0.4%
‘1010’ = ±0.5%
‘1011’ = ±0.6%
‘1100’ = ±0.8%
‘1101’ = ±1.0%
‘1110’ = ±1.25%
‘1111’ = ±1.5%
60
S2
50
S1
40
S0
3
1
96_100 SEL
Software select 96_100_SSC output frequency, 0 = 96 MHz, 1 = 100 MHz.
2
1
96_100 Enable
96_100_SSC Enable, 0 = Disable, 1 = Enable.
1
96_100 SS Enable
96_100_SSC Spread spectrum enable. 0 = Disable, 1 = Enable.
0
96_100 SW HW
Select output frequency of 96_100_SSC via software or hardware
0 = Hardware, 1 = Software.
Byte 10: Control Register 10
Bit
@Pup
Name
Description
7
0
RESERVED
6
0
CLKREQ#B
SRC[T/C]4 CLKREQ#B control
1 = SRC[T/C]4 stoppable by CLKREQ#B pin
0 = SRC[T/C]4not controlled by CLKREQ#B pin
5
0
CLKREQ#B
SRC[T/C]2 CLKREQ#B control
1 = SRC[T/C]2 stoppable by CLKREQ#B pin
0 = SRC[T/C]2 not controlled by CLKREQ#B pin
4
0
RESERVED
3
0
CLKREQ#A
SRC[T/C]7CLKREQ#A control
1 = SRC[T/C]7 stoppable by CLKREQ#A pin
0 = SRC[T/C]7 not controlled by CLKREQ#A pin
2
0
CLKREQ#A
SRC[T/C]5 CLKREQ#A control
1 = SRC[T/C]5 stoppable by CLKREQ#A pin
0 = SRC[T/C]5 not controlled by CLKREQ#A pin
1
0
CLKREQ#A
SRC[T/C]3 CLKREQ#A control
1 = SRC[T/C]3 stoppable by CLKREQ#A pin
0 = SRC[T/C]3 not controlled by CLKREQ#A pin
0
CLKREQ#A
SRC[T/C]1 CLKREQ#A control
1 = SRC[T/C]1 stoppable by CLKREQ#A pin
0 = SRC[T/C]1 not controlled by CLKREQ#A pin
Byte 8: Control Register 8 (continued)
Bit
@Pup
Name
Description
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY28442ZXCT | 功能描述:IC CLOCK GEN ALVISO 56-TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標(biāo)準(zhǔn)包裝:96 系列:- 類型:時鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
| CY28443 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Clock Generator for Intel㈢ Calistoga Chipset |
| CY28443-2 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Clock Generator for Intel㈢ Calistoga Chipset |
| CY28443-3 | 制造商:SPECTRALINEAR 制造商全稱:SPECTRALINEAR 功能描述:Clock Generator for Intel㈢ Calistoga Chipset |
| CY28443OXC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Clock Generator for Intel㈢ Calistoga Chipset |
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