參數(shù)資料
型號(hào)： CY28446LFXC
廠商： SILICON LABORATORIES
元件分類： 時(shí)鐘產(chǎn)生/分配
英文描述： 200 MHz, PROC SPECIFIC CLOCK GENERATOR, QCC64
封裝： 9 X 9 MM, LEAD FREE, MO-220, QFN-64
文件頁(yè)數(shù)： 19/19頁(yè)
文件大?。?/td> 174K
代理商： CY28446LFXC
CY28446
Rev 1.0, November 20, 2006
Page 9 of 19
is in series with the crystal. The total capacitance on both side
is twice the specified crystal load capacitance (CL). Trim
capacitors are calculated to provide equal capacitive loading
on both sides.
Use the following formulas to calculate the trim capacitor
values for Ce1 and Ce2.
CL....................................................Crystal load capacitance
CLe......................................... Actual loading seen by crystal
using standard value trim capacitors
Ce..................................................... External trim capacitors
Cs .............................................. Stray capacitance (terraced)
Ci ...........................................................Internal capacitance
(lead frame, bond wires etc.)
OE# Description
The OE# signals are active LOW inputs used for clean
enabling and disabling selected SRC outputs. The outputs
controlled by OE[A,B]# are determined by the settings in
register byte 3 and byte 8. OE[0,1,3,6]# controls SRC[0,1,3,6],
respectively. The OE# signal is a debounced signal and its
state must remain unchanged during two consecutive rising
edges of SRCC to be recognized as a valid assertion or
deassertion. (The assertion and deassertion of this signal is
absolutely asynchronous.)
OE# Assertion (OE# -> LOW)
All differential stopped outputs resume normal operation in a
glitch-free manner. The maximum latency from the assertion
to active outputs is between 2 and 6 SRC clock periods (2
clocks are shown) with all SRC outputs resuming simulta-
neously. All stopped SRC outputs must be driven HIGH within
10 ns of OE# deassertion to a voltage er than 200 mV.
OE# Deassertion (OE# -> HIGH)
The impact of deasserting the OE# pins is that all SRC outputs
that are set in the control registers to stoppable via deassertion
of OE# are stopped after their next transition. The final state
of all stopped SRC clocks is Low/low.
XTAL
Ce2
Ce1
Cs1
Cs2
X1
X2
Ci1
Ci2
Clock Chip
Trace
2.8 pF
Trim
33 pF
Pin
3 to 6p
Figure 2. Crystal Loading Example
Load Capacitance (each side)
Total Capacitance (as seen by the crystal)
Ce = 2 * CL – (Cs + Ci)
Ce1 + Cs1 + Ci1
1
+
Ce2 + Cs2 + Ci2
1
()
1
=
CLe
SRCT(stoppable)
SRCC(free running)
SRCT(free running)
OE#
Figure 3. OE# Deassertion/Assertion Waveform
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