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參數(shù)資料
| 型號： | CY3692 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | SCREWDRIVER, XONIC SLOT 3 X 100SCREWDRIVER, XONIC SLOT 3 X 100; Tip Size A x B:3 x 0.5mm; Tip size:3mm; Length, blade:100mm; Length, Inches:4"; Handle type:SHATTERPROOF CELLULOSE ACETATE; Tip Size:3 mm; Tip type:Parallel Slot |
| 中文描述： | 200 - MHz的現(xiàn)場可編程零延遲緩沖器 |
| 文件頁數(shù)： | 3/10頁 |
| 文件大小： | 201K |
| 代理商： | CY3692 |
CY23FP12
Document #: 38-07246 Rev. *E
Page 3 of 10
Below is a list of independent functions that can be
programmed with a volume or prototype programmer on the
“default” silicon.
/1,/2,/3,/4,
/x,/2x
/1,/2,/3,/4,
/x,/2x
/1,/2,/3,/4,
/x,/2x
/1,/2,/3,/4,
/x,/2x
/1,/2,/3,/4,
/x,/2x
/1,/2,/3,/4,
/x,/2x
PLL
/M
/N
Output
Function
Select
Matrix
REF
FBK
CLKB5
CLKB4
CLKB3
CLKB2
CLKB1
CLKB0
CLKA5
CLKA4
CLKA3
CLKA2
CLKA1
CLKA0
Figure 1. Basic PLL Block Diagram
Table 1.
Configuration
Description
Default
+16 mA
DC Drive Bank A
Programs the drive strength of Bank A outputs. The user can select one out
of two possible drive strength settings that produce output DC currents in the
range of ±16 mA to ±20 mA.
Programs the drive strength of Bank B outputs. The user can select one out
of two possible drive strength settings that produce output DC currents in the
range of ±16 mA to ±20 mA.
Enables/Disables CLKB[5:0] outputs. Each of the six outputs can be disabled
individually
if not used, to minimize electromagnetic interference (EMI) and
switching noise.
Enables/Disables CLKA[5:0] outputs. Each of the six outputs can be disabled
individually
if not used, to minimize EMI and switching noise.
Generates an inverted clock on the CLKA0 output. When this option is
programmed, CLKA0 and CLKA1 will become complimentary pairs.
Generates an inverted clock on the CLKA2 output. When this option is
programmed, CLKA2 and CLKA3 will become complimentary pairs.
Generates an inverted clock on the CLKA4 output. When this option is
programmed, CLKA4 and CLKA5 will become complimentary pairs.
Generates an inverted clock on the CLKB0 output. When this option is
programmed, CLKB0 and CLKB1 will become complimentary pairs.
Generates an inverted clock on the CLKB2 output. When this option is
programmed, CLKB2 and CLKB3 will become complimentary pairs.
DC Drive Bank B
+16 mA
Output Enable for Bank B clocks
Enable
Output Enable for Bank A clocks
Enable
Inv CLKA0
Non-invert
Inv CLKA2
Non-invert
Inv CLKA4
Non-invert
Inv CLKB0
Non-invert
Inv CLKB2
Non-invert
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY3693 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:PTG Programming Kit |
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| CY3695 | 功能描述:插座和適配器 Socket Adapter RoHS:否 制造商:Silicon Labs 產(chǎn)品:Adapter 用于:EM35x |
| CY3696 | 功能描述:插座和適配器 Socket Adapter RoHS:否 制造商:Silicon Labs 產(chǎn)品:Adapter 用于:EM35x |
| CY3697 | 功能描述:插座和適配器 Socket Adapter RoHS:否 制造商:Silicon Labs 產(chǎn)品:Adapter 用于:EM35x |
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