參數(shù)資料
型號(hào)： CY3764VP208-200UXC
廠商： Cypress Semiconductor Corp.
英文描述： BATT SEALED LEAD ACID 12V 2.3AH
中文描述： 為5V，3.3V，ISRTM高性能的CPLD
文件頁(yè)數(shù)： 9/64頁(yè)
文件大?。?/td> 1798K
代理商： CY3764VP208-200UXC
Ultra37000 CPLD Family
Document #: 38-03007 Rev. *D
Page 17 of 64
Parameter[11]
VX
Output Waveform—Measurement Level
tER(–)
1.5V
tER(+)
2.6V
tEA(+)
1.5V
tEA(–)
Vthe
(d) Test Waveforms
VOH
VX
0.5V
VOL
VX
0.5V
VX
VOH
0.5V
VX
VOL
0.5V
Switching Characteristics Over the Operating Range [12]
Parameter
Description
Unit
Combinatorial Mode Parameters
tPD
Input to Combinatorial Output
ns
tPDL
Input to Output Through Transparent Input or Output Latch
ns
tPDLL
Input to Output Through Transparent Input and Output Latches
ns
tEA
Input to Output Enable
ns
tER
Input to Output Disable
ns
Input Register Parameters
tWL
Clock or Latch Enable Input LOW Time[8]
ns
tWH
Clock or Latch Enable Input HIGH Time[8]
ns
tIS
Input Register or Latch Set-up Time
ns
tIH
Input Register or Latch Hold Time
ns
tICO
Input Register Clock or Latch Enable to Combinatorial Output
ns
tICOL
Input Register Clock or Latch Enable to Output Through Transparent Output Latch
ns
Synchronous Clocking Parameters
tCO
Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable to Output
ns
tS
Set-Up Time from Input to Sync. Clk (CLK0, CLK1, CLK2, or CLK3) or Latch Enable
ns
tH
Register or Latch Data Hold Time
ns
tCO2
Output Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable to Combinatorial Output
Delay (Through Logic Array)
ns
tSCS
Output Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable to Output Synchronous
Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable (Through Logic Array)
ns
tSL
Set-Up Time from Input Through Transparent Latch to Output Register Synchronous Clock (CLK0
CLK1, CLK2, or CLK3) or Latch Enable
ns
tHL
Hold Time for Input Through Transparent Latch from Output Register Synchronous Clock (CLK0,
CLK1, CLK2, or CLK3) or Latch Enable
ns
Notes:
11. tER measured with 5-pF AC Test Load and tEA measured with 35-pF AC Test Load.
12. All AC parameters are measured with two outputs switching and 35-pF AC Test Load.
13. Logic Blocks operating in Low-Power Mode, add tLP to this spec.
14. Outputs using Slow Output Slew Rate, add tSLEW to this spec.
15. When VCCO = 3.3V, add t3.3IO to this spec.
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