參數(shù)資料
型號(hào)： CY38030V256-66BBI
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： PLD
英文描述： LOADABLE PLD, 18.9 ns, PBGA256
封裝： 17 X 17 MM, 1.60 MM HEIGHT, TFBGA-256
文件頁(yè)數(shù)： 8/32頁(yè)
文件大小： 929K
代理商： CY38030V256-66BBI
PRELIMINARY
Quantum38K ISR
CPLD Family
Document #: 38-03043 Rev. **
Page 16 of 32
Channel Memory Timing Parameter Descriptions Over the Operating Range
Parameter
Description
Dual Port Asynchronous Mode Parameters
tCHMAA
Channel memory access time. Delay from address change to read data out
tCHMPWE
Write enable pulse width
tCHMSA
Address set-up to the beginning of write enable
tCHMHA
Address hold after the end of write enable with both signals from the same I/O block
tCHMSD
Data set-up to the end of write enable
tCHMHD
Data hold after the end of write enable
tCHMBA
Channel memory asynchronous dual port address match (busy access time)
Dual Port Synchronous Mode Parameters
tCHMCYC1
Clock cycle time for flow through read and write operations (from macrocell register through channel
memory back to a macrocell register in the same cluster)
tCHMCYC2
Clock cycle time for pipelined read and write operations (from channel memory input register through the
memory to channel memory output register)
tCHMS
Address, data, and WE set-up time of pin inputs, relative to a global clock
tCHMH
Address, data, and WE hold time of pin inputs, relative to a global clock
tCHMDV1
Global clock to data valid on output pins for flow through data
tCHMDV2
Global clock to data valid on output pins for pipelined data
tCHMBDV
Channel memory synchronous dual-port address match (busy, clock to data valid)
tCHMMACS1
Channel memory input clock to macrocell clock in the same cluster
tCHMMACS2
Channel memory output clock to macrocell clock in the same cluster
tMACCHMS1
Macrocell clock to channel memory input clock in the same cluster
tMACCHMS2
Macrocell clock to channel memory output clock in the same cluster
Internal Parameters
tCHMCHAA
Asynchronous channel memory access time from input of channel memory to output of channel memory
相關(guān)PDF資料
PDF描述
CY38050V208-83NC LOADABLE PLD, 15 ns, PQFP208
CY38050V256-83BBC LOADABLE PLD, 15 ns, PBGA256
CY38050V484-83BBC LOADABLE PLD, 15 ns, PBGA484
CY38050V208-125NC LOADABLE PLD, 10 ns, PQFP208
CY38050V208-125NI LOADABLE PLD, 10 ns, PQFP208
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參數(shù)描述
CY38050V208-125NTC 制造商:Cypress Semiconductor 功能描述:CPLD QUANTUM38K 72K GATES 768 MCRCLLS COMM 0.18UM 2.5V/3.3V - Bulk
CY38050V208-125NTI 制造商:Cypress Semiconductor 功能描述:CPLD QUANTUM38K 72K GATES 768 MCRCLLS IND 0.18UM 2.5V/3.3V 2 - Bulk
CY38050V208-83NTC 制造商:Cypress Semiconductor 功能描述:CPLD QUANTUM38K 72K GATES 768 MCRCLLS COMM 0.18UM 2.5V/3.3V - Bulk
CY38050V208-83NTI 制造商:Cypress Semiconductor 功能描述:CPLD QUANTUM38K 72K GATES 768 MCRCLLS IND 0.18UM 2.5V/3.3V 2 - Bulk
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