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參數(shù)資料
| 型號： | CY38050V208-83NC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | LOADABLE PLD, 15 ns, PQFP208 |
| 封裝： | PLASTIC, QFP-208 |
| 文件頁數(shù)： | 34/45頁 |
| 文件大?。?/td> | 720K |
| 代理商： | CY38050V208-83NC |
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Quantum38K ISR
CPLD Family
Document #: 38-03043 Rev. *G
Page 4 of 45
General Description
The Quantum38K family, based on a 0.18-mm, six-layer metal
CMOS logic process, offers a wide range of solutions at very
high system performance. With devices ranging from 512 to
1536 macrocells, Quantum38K is the highest density CPLD in
the market besides Cypress’s Delta39K. Specifically designed
to address high-volume communication applications, this
family also integrates Cypress’s dual-port memory technology
onto a CPLD.
The architecture is based on Logic Block Clusters (LBC) that
are connected by Horizontal and Vertical (H&V) routing
channels. Each LBC features eight individual Logic Blocks
(LB). Adjacent to each LBC is a channel memory block, which
can be accessed directly from the I/O pins. These channel
memory blocks are highly configurable and can be cascaded
in width and depth. See Figure 1 for a block diagram of the
Quantum38K architecture.
All the members of the Quantum38K family have Cypress’s
highly regarded In-System Reprogrammability (ISR) feature,
which simplifies both design and manufacturing flows, thereby
reducing costs. The ISR feature provides the ability to recon-
figure the devices without having design changes cause
pinout or timing changes in most cases. The Cypress ISR
function is implemented through a JTAG-compliant serial
interface. Data is shifted in and out through the TDI and TDO
pins respectively. Superior routability, simple timing, and the
ISR allows users to change existing logic designs while simul-
taneously fixing pinout assignments and maintaining system
performance.
The entire family features JTAG for ISR and boundary scan,
and is compatible with the PCI Local Bus specification,
meeting
the
electrical
and
timing
requirements.
The
Quantum38K
family
also
features
user
programmable
bus-hold and slew rate control capabilities on each I/O pin.
AnyVolt Interface
All Quantum38K devices feature an on-chip regulator, which
accepts 3.3V or 2.5V on the VCC supply pins and steps it down
to 1.8V internally, the voltage level at which the core operates.
With Quantum38K’s AnyVolt technology, the I/O pins can be
connected to either 1.8V 2.5V, or 3.3V. All Quantum38K
devices are 3.3V tolerant regardless of VCCIO or VCC settings.
Global Routing Description
The routing architecture of the Quantum38K is made up of
H&V routing channels. These routing channels allow signals
from each of the Quantum38K architectural components to
communicate with one another. In addition to the horizontal
and vertical routing channels that interconnect the I/O banks,
channel memory blocks, and logic block clusters, each LBC
contains a Programmable Interconnect Matrix (PIM), which
is used to route signals among the logic blocks.
Figure 2 is a block diagram of the routing channels that
interface within the Quantum38K architecture. The LBC is
exactly the same for every member of the Quantum38K CPLD
family.
Logic Block Cluster (LBC)
The Quantum38K architecture consists of several logic block
clusters, each of which have eight Logic Blocks (LB)
connected via a PIM, as shown in Figure 3. All LBCs interface
with each other via horizontal and vertical routing channels.
Device
VCC
VCCIO
38K
3.3V or 2.5V
3.3V or 2.5V or 1.8V
Figure 2. Quantum38K Routing Interface
LB
Cluster
PIM
Cluster
Memory
Block
LB
Cluster
Memory
Block
LB
Channel
Memory
Block
I/O Block
I/O
B
lock
Channel memory
outputs drive
dedicated tracks in the
horizontal and vertical
routing channels
H-to-V
PIM
V-to-H
PIM
Pin inputs from the I/O cells
drive dedicated tracks in the
horizontal and vertical routing
channels
72
64
LB
相關PDF資料 |
PDF描述 |
|---|---|
| CY38050V256-83BBC | LOADABLE PLD, 15 ns, PBGA256 |
| CY38050V484-83BBC | LOADABLE PLD, 15 ns, PBGA484 |
| CY38050V208-125NC | LOADABLE PLD, 10 ns, PQFP208 |
| CY38050V208-125NI | LOADABLE PLD, 10 ns, PQFP208 |
| CY38050V256-125BBC | LOADABLE PLD, 10 ns, PBGA256 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CY38050V208-83NTC | 制造商:Cypress Semiconductor 功能描述:CPLD QUANTUM38K 72K GATES 768 MCRCLLS COMM 0.18UM 2.5V/3.3V - Bulk |
| CY38050V208-83NTI | 制造商:Cypress Semiconductor 功能描述:CPLD QUANTUM38K 72K GATES 768 MCRCLLS IND 0.18UM 2.5V/3.3V 2 - Bulk |
| CY38100V208-125NTI | 制造商:Cypress Semiconductor 功能描述:CPLD QUANTUM38K 144K GATES 1536 MCRCLLS IND 0.18UM 2.5V/3.3V - Bulk |
| CY3858-000 | 制造商:TE Connectivity 功能描述:2524F0524-1L/9-9-L016 - Cable Rools/Shrink Tubing |
| CY39 | 制造商:PLETRONICS 制造商全稱:Pletronics, Inc. 功能描述:Crystals |
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