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參數(shù)資料
| 型號(hào)： | CY38050V208-83NC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | LOADABLE PLD, 15 ns, PQFP208 |
| 封裝： | PLASTIC, QFP-208 |
| 文件頁數(shù)： | 45/45頁 |
| 文件大小： | 720K |
| 代理商： | CY38050V208-83NC |
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Quantum38K ISR
CPLD Family
Document #: 38-03043 Rev. *G
Page 9 of 45
In addition, there are six Output Control Channel (OCC)
signals available to each I/O cell. These control signals may
be used as output enables, register resets and register clock
enables as shown in Figure 7. Unlike global control signals,
these OCC signal can be driven from internal logic or and I/O
pin.
One of the four global clocks can be selected as the clock for
the I/O cell register. The clock mux output is an input to a clock
polarity mux that allows the input/output register to be clocked
on either edge of the clock.
Slew Rate Control
The ouput buffer has a slew rate control option. This allows the
output buffer to slew at a fast rate (3 V/ns) or a slow rate
(1 V/ns). All I/Os default to fast slew rate. For designs
concerned with meeting FCC emissions standards the slow
edge provides for lower system noise. For designs requiring
very high performance the fast edge rate provides maximum
system performance.
Programmable Bus Hold
On each I/O pin, user-programmable-bus-hold is included.
Bus-hold, which is an improved version of the popular internal
pull-up resistor, is a weak latch connected to the pin that does
not degrade the device’s performance. As a latch, bus-hold
maintains the last state of a pin when the pin is placed in a
high-impedance state, thus reducing system noise in
bus-interface
applications.
Bus-hold
additionally
allows
unused device pins to remain unconnected on the board,
which is particularly useful during prototyping as designers can
route new signals to the device without cutting trace connec-
tions to VCC or GND. For more information, see the application
note “Understanding Bus-Hold–A Feature of Cypress CPLDs”.
Clocks
Quantum38K has four dedicated clock input pins (GCLK[3:0])
to accept system clocks.
The global clock tree for a Quantum38K device is driven by the
dedicated clock pins, consisting of four global clocks that go to
every macrocell, memory block, and I/O cell.
Clock Tree Distribution
The clock tree distributes the four global clocks to every
cluster, channel memory, and I/O block on the die. The global
clock tree is designed such that the clock skew is minimized
while maintaining an acceptable clock delay.
CompactPCI Hot Swap
CompactPCI Hot Swap specification allows the removal and
insertion
of
cards
into
CompactPCI
sockets
without
switching-off the bus. Quantum38K CPLDs can be used as a
CompactPCI host or target on these cards.
This feature is useful in telecommunication and networking
applications as it allows implementation of high availability
systems, where repairs and upgrades can be done without
downtime.
Quantum38K CPLDs are CompactPCI Hot Swap Ready per
CompactPCI Hot Swap specification R1.0, with the following
exception:
IO Standards
I/O Standard
VCCIO
LVTTL (2 mA – 24 mA)
3.3V
LVCMOS
3.3V
LVCMOS3
3.0V
LVCMOS2
2.5V
LVCMOS18
1.8V
3.3V PCI
3.3V
Figure 7. Block Diagram of I/O Cell
DQ
RES
E
G
lobal
I/O
C
ontr
o
lSi
gnal
s
O
u
tput
C
ontr
o
lC
hannel
O
C
G
lobal
C
loc
k
Si
gnal
s
Slew
Rate
Control
C
I/O
From
Output PIM
To Routing
Channel
OE Mux
Register Input
Mux
Register Enable
Mux
Output Mux
Clock Mux
Clock
Polarity
Mux
Register Reset
Mux
Input
Mux
Bus
Hold
C
DQ
RES
C
Registered OE
Mux
C
3
C
3
C
2
3
C
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PDF描述 |
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| CY38050V484-83BBC | LOADABLE PLD, 15 ns, PBGA484 |
| CY38050V208-125NC | LOADABLE PLD, 10 ns, PQFP208 |
| CY38050V208-125NI | LOADABLE PLD, 10 ns, PQFP208 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY38050V208-83NTC | 制造商:Cypress Semiconductor 功能描述:CPLD QUANTUM38K 72K GATES 768 MCRCLLS COMM 0.18UM 2.5V/3.3V - Bulk |
| CY38050V208-83NTI | 制造商:Cypress Semiconductor 功能描述:CPLD QUANTUM38K 72K GATES 768 MCRCLLS IND 0.18UM 2.5V/3.3V 2 - Bulk |
| CY38100V208-125NTI | 制造商:Cypress Semiconductor 功能描述:CPLD QUANTUM38K 144K GATES 1536 MCRCLLS IND 0.18UM 2.5V/3.3V - Bulk |
| CY3858-000 | 制造商:TE Connectivity 功能描述:2524F0524-1L/9-9-L016 - Cable Rools/Shrink Tubing |
| CY39 | 制造商:PLETRONICS 制造商全稱:Pletronics, Inc. 功能描述:Crystals |
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