參數(shù)資料
型號： CY38050V256-125BBC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： PLD
英文描述： LOADABLE PLD, 10 ns, PBGA256
封裝： 17 X 17 MM, FBGA-256
文件頁數(shù)： 6/45頁
文件大?。?/td> 720K
代理商： CY38050V256-125BBC
Quantum38K ISR
CPLD Family
Document #: 38-03043 Rev. *G
Page 14 of 45
Power-up Sequence Requirements
Upon power-up, all the outputs remain three-stated until all
the VCC pins have powered-up to the nominal voltage and
the part has completed configuration.
The part will not start configuration until VCC, VCCIO,
VCCJTAG, and VCCCNFG have reached nominal voltage.
VCC pins can be powered up in any order. This includes
VCC, VCCIO, VCCJTAG, and VCCCNFG.
All VCCIOs on a bank should be tied to the same potential
and powered up together.
All VCCIOs (even the unused banks) need to be powered up
to at least 1.5V before configuration has completed.
Maximum ramp time for all VCCs should be 0V to nominal
voltage in 100 ms.
Notes:
7.
PCI spec (rev 2.2) requires the IDSEL pin to have capacitance less than or equal to 8 pF. Section titled “Pin Tables” on page 27 identifies all the I/O pins, in a
given package, which can be used as IDSEL in a PCI design. All other I/O pins meet the PCI requirement of capacitance less than or equal to 10 pF.
8.
The number of I/Os that can be used in each I/O bank depends on the type of I/O standards and the number of VCCIO and GND pins being used. Please refer
to the application note titled “Delta39K and Quantum38K I/O Standards and Configurations” for details.
The source current limit per I/O bank per VCCIO pin is 165 mA.
The sink current limit per I/O bank per GND pin is 230 mA.
Capacitance
Parameter
Description
Test Conditions
Min.
Max.
Unit
CI/O
Input/Output Capacitance
Vin=VCCIO @ f = 1 MHz 25°C
10
pF
CCLK
Clock Signal Capacitance
Vin=VCCIO @ f = 1 MHz 25°C
5
12
pF
CPCI
PCI-compliant[7] Capacitance
Vin=VCCIO @ f = 1 MHz 25°C
8
pF
DC Characteristics[8] (IO)
Input/Output
Standard
VCCIO
(V)
VOH (V)
VOL (V)
VIH (V)
VIL (V)
@ IOH =VOH (min.)
@ IOL =
VOL
(max.)
Min.
Max.
Min.
Max.
LVTTL – 2 mA
3.3
–2 mA
2.4
2 mA
0.4
2.0 V
VCCIO+0.3
–0.3V
0.8V
LVTTL – 4 mA
3.3
–4 mA
2.4
4 mA
0.4
2.0 V
VCCIO+0.3
–0.3V
0.8V
LVTTL – 6 mA
3.3
–6 mA
2.4
6 mA
0.4
2.0 V
VCCIO+0.3
–0.3V
0.8V
LVTTL – 8 mA
3.3
–8 mA
2.4
8 mA
0.4
2.0 V
VCCIO+0.3
–0.3V
0.8V
LVTTL – 12 mA
3.3
–12 mA
2.4
12 mA
0.4
2.0 V
VCCIO+0.3
–0.3V
0.8V
LVTTL – 16 mA
3.3
–16 mA
2.4
16 mA
0.4
2.0 V
VCCIO+0.3
–0.3V
0.8V
LVTTL – 24 mA
3.3
–24 mA
2.4
24 mA
0.4
2.0 V
VCCIO+0.3
–0.3V
0.8V
LVCMOS
3.3
–0.1 mA
VCCIO–0.2v
0.1 mA
0.2
2.0 V
VCCIO+0.3
–0.3V
0.8V
LVCMOS3
3.0
–0.1 mA
VCCIO–0.2v
0.1mA
0.2
2.0 V
VCCIO+0.3
–0.3V
0.8V
LVCMOS2
2.5
–0.1 mA
2.1
0.1 mA
0.2
1.7 V
VCCIO+0.3
–0.3V
0.7V
–1.0 mA
2.0
1.0 mA
0.4
–2.0 mA
1.7
2.0 mA
0.7
LVCMOS18
1.8
–0.1 mA
VCCIO–0.2v
0.1 mA
0.2
0.65VCCIO
VCCIO+0.3
–0.3V
0.35VCCIO
–2 mA
VCCIO–0.45v
2.0 mA
0.45
3.3V PCI
3.3
–0.5 mA
0.9VCCIO
1.5 mA
0.1VCCIO
0.5VCCIO
VCCIO+0.5
–0.5V
0.3VCCIO
Configuration Parameters
Parameter
Description
Min.
Unit
tRECONFIG
Reconfig pin LOW time before it goes HIGH
200
ns
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