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| 型號： | CY38050V256-83BBC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | LOADABLE PLD, 15 ns, PBGA256 |
| 封裝： | 17 X 17 MM, FBGA-256 |
| 文件頁數(shù)： | 41/45頁 |
| 文件大?。?/td> | 720K |
| 代理商： | CY38050V256-83BBC |
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Quantum38K ISR
CPLD Family
Document #: 38-03043 Rev. *G
Page 5 of 45
Logic Block (LB)
The logic block is the basic building block of the Quantum38K
architecture. It consists of a product term array, an intelligent
product-term allocator, and 16 macrocells.
Product Term Array
Each logic block features a 72 x 83 programmable product
term array. This array accepts 36 inputs from the PIM. These
inputs originate from device pins and macrocell feedbacks as
well as channel memory feedbacks. Active LOW and active
HIGH versions of each of these inputs are generated to create
the full 72-input field. The 83 product terms in the array can be
created from any of the 72 inputs.
Of the 83 product terms, 80 are for general-purpose use for
the 16 macrocells in the logic block. Two of the remaining three
product terms in the logic block are used as asynchronous set
and asynchronous reset product terms. The final product term
is the Product Term clock (PTCLK) and is shared by all 16
macrocells within a logic block.
Product Term Allocator
Through the product term allocator, Warp software automati-
cally distributes the 80 product terms as needed among the 16
macrocells in the logic block. The product term allocator
provides two important capabilities without affecting perfor-
mance: product term steering and product term sharing.
Product Term Steering
Product term steering is the process of assigning product
terms to macrocells as needed. For example, if one macrocell
requires ten product terms while another needs just three, the
product term allocator will “steer” ten product terms to one
macrocell and three to the other. On Quantum38K devices,
product terms are steered on an individual basis. Any number
between 1 and 16 product terms can be steered to any
macrocell.
Product Term Sharing
Product term sharing is the process of using the same product
term among multiple macrocells. For example, if more than
one function has one or more product terms in its equation that
are common to other functions, those product terms are only
programmed once. The Quantum38K product term allocator
allows sharing across groups of four macrocells in a variable
fashion. The software automatically takes advantage of this
capability so that the user does not have to intervene.
Note that neither product term sharing nor product term
steering have any effect on the speed of the product. All
steering and sharing configurations have been incorporated in
the timing specifications for the Quantum38K devices.
Macrocell
Within each logic block there are 16 macrocells. Each
macrocell accepts a sum of up to 16 product terms from the
product term array. The sum of these 16 product terms can be
output in either registered or combinatorial mode. Figure 4
displays the block diagram of the macrocell. The register can
be asynchronously preset or asynchronously reset at the
macrocell level with the separate preset and reset product
terms. Each of these product terms features programmable
polarity. This allows the registers to be preset or reset based
on an AND expression or an OR expression.
An XOR gate in the Quantum38K macrocell allows for many
different types of equations to be realized. It can be used as a
polarity mux to implement the true or complement form of an
equation in the product term array or as a toggle to turn the D
flip-flop into a T flip-flop. The carry-chain input mux allows
additional flexibility for the implementation of different types of
logic. The macrocell can utilize the carry chain logic to
Figure 3. Quantum38K Logic Block Cluster Diagram
Logic
Block
0
Logic
Block
1
Logic
Block
3
Logic
Block
2
Cluster
Memory
0
PIM
Logic
Block
7
Logic
Block
6
Logic
Block
4
Logic
Block
5
Cluster
Memory
1
64 Inputs From
Horizontal Routing
64 Inputs From
Vertical Routing
Channel
Clock Inputs
GCLK[3:0]
CC
CC = Carry Chain
16
36
16
36
16
36
16
36
16
36
16
36
16
36
8
25
8
25
4
16
36
64 Inputs from
Horizontal Routing
Channel
144 Outputs to
Horizontal and Vertical
Cluster-to-Channel PIMs
64 Inputs from
Vertical Routing
Channel
16
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| CY38050V256-125BBI | LOADABLE PLD, 10 ns, PBGA256 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CY38100V208-125NTI | 制造商:Cypress Semiconductor 功能描述:CPLD QUANTUM38K 144K GATES 1536 MCRCLLS IND 0.18UM 2.5V/3.3V - Bulk |
| CY3858-000 | 制造商:TE Connectivity 功能描述:2524F0524-1L/9-9-L016 - Cable Rools/Shrink Tubing |
| CY39 | 制造商:PLETRONICS 制造商全稱:Pletronics, Inc. 功能描述:Crystals |
| CY3900I | 功能描述:開發(fā)軟件 ISR Programming Kit RoHS:否 制造商:Atollic Inc. 產品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| CY3900I_05 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Delta39K⑩⁄Ultra37000⑩ ISR⑩ Programming Kits |
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