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| 型號： | CY39200Z484-167BBC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | LOADABLE PLD, 8.5 ns, PBGA484 |
| 封裝： | 23 X 23 MM, 1.60 MM HEIGHT, 1 MM PITCH, TFBGA-484 |
| 文件頁數(shù)： | 4/57頁 |
| 文件大小： | 1166K |
| 代理商： | CY39200Z484-167BBC |
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PRELIMINARY
Delta39K ISR
CPLD Family
Document #: 38-03039 Rev. **
Page 12 of 57
Table 4 describes the valid phase shift options that can be used
with or without an external feedback.
Table 5 is an example of the effect of all the available divide
and phase shift options on a VCO output of 250 MHz. It also
shows the effect of division on the duty cycle of the resultant
clock. Note that the duty cycle is 50-50 when a VCO output is
divided by an even number. Also note that the phase shift ap-
plies to the VCO output and not to the divided output.
The Spread Aware PLL operates as specified for Delta39KV
devices (2.5V/3.3V), but not Delta39KZ devices (1.8V). For
more details on the architecture and operation of this PLL
please refer to the application note entitled “Delta39K PLL and
Clock Tree.”
Table 3. PLL Multiply and Divide Options—with External Feedback
Input (GCLK) Frequency
fPLLI (MHz)
Valid Multiply Options
Valid Divide Options
Value
VCO Output
Frequency (MHz)
Value
Output (INTCLK) Frequency
fPLLO (MHz)
Off-chip Clock
Frequency
50–66
1
100–133
1
100–133
50–66
66–100
1
133–200
1
133–200
66–100
100–133
1
200–266
1
200–266
100–133
Table 4. PLL Phase Shift Options—
with and without External Feedback
Without External Feedback
With External
Feedback
0°,45°, 90°, 135°, 180°, 225°, 270°, 315°
0°
Table 5. Timing of Clock Phases for all Divide Options for a VCO Output Frequency of 250 MHz
Divide
Factor
Period
(ns)
Duty
Cy-
cle%
0°
(ns)
45°
(ns)
90°
(ns)
135°
(ns)
180°
(ns)
225°
(ns)
270°
(ns)
315°
(ns)
1
4
40-60
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
2
8
50
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
3
12
33-67
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4
16
50
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
5
20
40-60
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
6
24
50
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
8
32
50
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
16
64
50
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
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