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參數(shù)資料
| 型號： | CY39200Z484-167BBC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | LOADABLE PLD, 8.5 ns, PBGA484 |
| 封裝： | 23 X 23 MM, 1.60 MM HEIGHT, 1 MM PITCH, TFBGA-484 |
| 文件頁數(shù)： | 46/57頁 |
| 文件大?。?/td> | 1166K |
| 代理商： | CY39200Z484-167BBC |
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PRELIMINARY
Delta39K ISR
CPLD Family
Document #: 38-03039 Rev. **
Page 50 of 57
Delta39K100 Revisions/Errata
Three revisions of Delta39K100, in 3.3V version, are currently
offered which are marked as CY39100Vxxx, CY39100VxxxA
and CY39100VxxxB. CY39100VxxxB devices operate exactly
as specified in this datasheet. Following paragraphs explain
the operation of the CY39100Vxxx and CY39100VxxxA parts
as different from this datasheet:
CY39100Vxxx
1. The internal regulator takes several seconds to power
down. Hence, cycling the power supply (within 8 seconds)
may cause a high standby current (200 mA to 1A) until the
part is configured.
2. The part always configures on power-up and will reconfig-
ure on HIGH to LOW edge of the Reconfig pin. Please refer
to the application note titled “Configuring
Delta39K/Quantum38K” at http://www.cypress.com for
more details.
3. The Self Config instruction starts reconfiguring the CPLD
upon execution of the Update-IR state of the JTAG TAP
controller state machine. In CY39100VxxxB parts, Self
Config instruction is executed upon execution of Test-Log-
ic-Reset state of the TAP controller.
4. An ESD failure is very unlikely. CDM ESD passes 1000V.
HBM ESD passes 3300V with all I/O bank’s VCCIO shorted
together. If VCCIOs in a bank are tested separately a per-
centage of parts will fail HBM ESD over 500V.
CY39100VxxxA
1. The part always configures on power-up and will reconfig-
ure on HIGH to LOW edge of the Reconfig pin. Please refer
to the application note titled “Configuring
Delta39K/Quantum38K” at http://www.cypress.com for
more details.
2. The Self Config instruction starts reconfiguring the CPLD
upon execution of the Update-IR state of the JTAG TAP
controller state machine. In CY39100VxxxB parts, Self
Config instruction is executed upon execution of Test-Log-
ic-Reset state of the TAP controller.
3. An ESD failure is very unlikely. CDM ESD passes 1000V.
HBM ESD passes 3300V with all I/O bank’s VCCIO shorted
together. If VCCIOs in a bank are tested separately a per-
centage of parts will fail HBM ESD over 500V.
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PDF描述 |
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| CY39200Z676-167MBC | LOADABLE PLD, 8.5 ns, PBGA676 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY39200Z676-125BBC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY39200Z676-125BBI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY39200Z676-125BGC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY39200Z676-125BGI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY39200Z676-125MBC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
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