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參數(shù)資料
| 型號(hào)： | CY62137CV33LL |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 2-Mbit (128K x 16) Static RAM |
| 中文描述： | 2兆位（128K的× 16）靜態(tài)RAM |
| 文件頁數(shù)： | 6/13頁 |
| 文件大小： | 339K |
| 代理商： | CY62137CV33LL |
CY62137CV30/33 MoBL
CY62137CV MoBL
Document #: 38-05201 Rev. *G
Page 6 of 13
Switching Characteristics
Over the Operating Range
[9]
Parameter
Description
55 ns
70 ns
Unit
Min.
Max.
Min.
Max.
Read Cycle
t
RC
Read Cycle Time
55
70
ns
t
AA
Address to Data Valid
55
70
ns
t
OHA
Data Hold from Address Change
10
10
ns
t
ACE
CE LOW to Data Valid
55
70
ns
t
DOE
OE LOW to Data Valid
25
35
ns
t
LZOE
OE LOW to Low-Z
[10]
5
5
ns
t
HZOE
OE HIGH to High-Z
[10, 12]
20
25
ns
t
LZCE
CE LOW to Low-Z
[10]
10
10
ns
t
HZCE
CE HIGH to High-Z
[10, 12]
20
25
ns
t
PU
CE LOW to Power-up
0
0
ns
t
PD
CE HIGH to Power-down
55
70
ns
t
DBE
t
LZBE[11]
BHE/BLE LOW to Data Valid
55
70
ns
BHE/BLE LOW to Low-Z
[10]
5
5
ns
t
HZBE
Write Cycle
[13]
BHE/BLE HIGH to High-Z
[10, 12]
20
25
ns
t
WC
Write Cycle Time
55
70
ns
t
SCE
CE LOW to Write End
45
60
ns
t
AW
Address Set-up to Write End
45
60
ns
t
HA
Address Hold from Write End
0
0
ns
t
SA
Address Set-up to Write Start
0
0
ns
t
PWE
WE Pulse Width
40
45
ns
t
BW
BHE/BLE Pulse Width
50
60
ns
t
SD
Data Set-up to Write End
25
30
ns
t
HD
Data Hold from Write End
0
0
ns
t
HZWE
WE LOW to High-Z
[10, 12]
20
25
ns
t
LZWE
WE HIGH to Low-Z
[10]
10
10
ns
Notes:
9. Test conditions assume signal transition time of 5 ns or less, timing reference levels of V
CC(typ.)
/2, input pulse levels of 0 to V
CC(typ.)
, and output loading of the
specified I
/I
and 30 pF load capacitance.
10.At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZBE
is less than t
LZBE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any
given device.
11. If both byte enables are toggled together this value is 10 ns.
12.t
, t
, t
, and t
transitions are measured when the outputs enter a high impedance state.
13.The internal write time of the memory is defined by the overlap of WE, CE
= V
, BHE and/or BLE = V
. All signals must be ACTIVE to initiate a write and any
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates
the write.
[+] Feedback
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| CY62137CV33LL-55BAI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2M (128K x 16) Static RAM |
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| CY62137CV33LL-55BVIT | 制造商:Cypress Semiconductor 功能描述: |
| CY62137CV33LL-70BAI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2M (128K x 16) Static RAM |
| CY62137CV33LL-70BVI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2M (128K x 16) Static RAM |
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