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參數(shù)資料
| 型號： | CY62147EV30LL-45ZSXI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 4-Mbit (256K x 16) Static RAM |
| 中文描述： | 256K X 16 STANDARD SRAM, 45 ns, PDSO44 |
| 封裝： | LEAD FREE, TSOP2-44 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 517K |
| 代理商： | CY62147EV30LL-45ZSXI |
CY62147EV30 MoBL
Document #: 38-05440 Rev. *E
Page 5 of 12
Switching Characteristics
Over the Operating Range
[12, 13]
Parameter
Description
45 ns (Ind’l/Auto-A)
55 ns (Auto-E)
Unit
Min
Max
Min
Max
Read Cycle
t
RC
Read Cycle Time
45
55
ns
t
AA
Address to Data Valid
45
55
ns
t
OHA
Data Hold from Address Change
10
10
ns
t
ACE
CE LOW to Data Valid
45
55
ns
t
DOE
OE LOW to Data Valid
22
25
ns
t
LZOE
OE LOW to LOW Z
[14]
5
5
ns
t
HZOE
OE HIGH to High Z
[14, 15]
18
20
ns
t
LZCE
CE LOW to Low Z
[14]
10
10
ns
t
HZCE
CE HIGH to High Z
[14, 15]
18
20
ns
t
PU
CE LOW to Power Up
0
0
ns
t
PD
CE HIGH to Power Down
45
55
ns
t
DBE
BLE/BHE LOW to Data Valid
45
55
ns
t
LZBE
BLE/BHE LOW to Low Z
[14]
10
10
ns
t
HZBE
Write Cycle
[16]
BLE/BHE HIGH to HIGH Z
[14, 15]
18
20
ns
t
WC
Write Cycle Time
45
55
ns
t
SCE
CE LOW to Write End
35
40
ns
t
AW
Address Setup to Write End
35
40
ns
t
HA
Address Hold from Write End
0
0
ns
t
SA
Address Setup to Write Start
0
0
ns
t
PWE
WE Pulse Width
35
40
ns
t
BW
BLE/BHE LOW to Write End
35
40
ns
t
SD
Data Setup to Write End
25
25
ns
t
HD
Data Hold from Write End
0
0
ns
t
HZWE
WE LOW to High-Z
[14, 15]
18
20
ns
t
LZWE
WE HIGH to Low-Z
[14]
10
10
ns
Notes
12.Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1V/ns) or less, timing reference levels of V
CC(typ)
/2, input
pulse levels of 0 to V
, and output loading of the specified I
/I
as shown in the
“AC Test Loads and Waveforms” on page 4
.
13.AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See
application note AN13842
for further clarification.
14.At any temperature and voltage condition, t
is less than t
, t
is less than t
, t
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any device.
15.t
, t
, t
, and t
transitions are measured when the outputs enter a high impedance state.
16.The internal write time of the memory is defined by the overlap of WE, CE
= V
, BHE, BLE, or both = V
. All signals must be active to initiate a write and any of
these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
[+] Feedback
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