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參數(shù)資料
| 型號： | CY62256-55SNC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 256K (32K x 8) Static RAM |
| 中文描述： | 32K X 8 STANDARD SRAM, 55 ns, PDSO28 |
| 封裝： | 0.300 INCH, SOIC-28 |
| 文件頁數(shù)： | 2/12頁 |
| 文件大?。?/td> | 394K |
| 代理商： | CY62256-55SNC |
CY62256
Document #: 38-05248 Rev. *C
Page 2 of 12
Product Portfolio
Pin Configurations
Pin Definitions
Product
V
CC
Range (V)
Typ.
[2]
5.0
Speed
(ns)
70
55/70
70
55/70
55
Power Dissipation
Operating, I
CC
(mA)
Typ.
[2]
Max.
28
55
25
50
25
50
25
50
25
50
Standby, I
SB2
(
μ
A)
Typ.
[2]
1
2
0.1
0.1
0.1
Min.
4.5
Max.
5.5
Max.
5
50
5
10
15
CY62256
CY62256L
CY62256LL
CY62256LL
CY62256LL
Commercial
Com’l / Ind’l
Commercial
Industrial
Automotive
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
20
19
18
17
21
24
23
22
Top View
Narrow SOIC
25
28
27
26
GND
A6
A7
A8
A9
A10
A11
A12
A13
A14
I/O0
I/O1
I/O2
WE
A
4
A3
A2
A1
OE
A0
VCC
I/O7
I/O6
I/O5
I/O4
I/O3
A5
CE
22
23
24
25
26
27
28
1
2
5
4
10
11
12
15
16
17
14
13
19
20
21
18
3
7
6
8
9
OE
A
1
A
2
A
3
4
A
V
CC
A
5
A
6
A
7
A
8
A
9
A
0
CE
7
I/O
6
I/O
5
I/O
3
GND
2
I/O
1
I/O
4
I/O
0
A
14
A
10
A
11
A
13
A
12
TSOP I
Top View
(not to scale)
Reverse Pinout
22
23
24
25
26
27
28
1
2
3
4
5
6
10
9
11
15
14
13
12
16
19
18
17
20
21
7
8
OE
A
1
A
2
A
3
A
4
WE
V
CC
5
A
6
A
7
A
8
A
9
A
10
A
11
A
0
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
GND
I/O
2
I/O
1
I/O
0
A
14
A
13
A
12
TSOP I
Top View
(not to scale)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
20
19
18
17
21
24
23
22
Top View
DIP
25
28
27
26
GND
A6
A7
A8
A9
A10
A11
A12
A13
A14
I/O0
I/O1
I/O2
WE
A
4
A3
A2
A1
OE
A0
VCC
I/O7
I/O6
I/O5
I/O4
I/O3
A5
CE
Pin Number
Type
Description
1-10, 21, 23-26
Input
A
0
-A
14
. Address Inputs
I/O
0
-I/O
7
. Data lines. Used as input or output lines depending on operation
WE
. When selected LOW, a WRITE is conducted. When selected HIGH, a READ is
conducted
11-13, 15-19,
Input/Output
27
Input/Control
20
Input/Control
CE
. When LOW, selects the chip. When HIGH, deselects the chip
22
Input/Control
OE
. Output Enable. Controls the direction of the I/O pins. When LOW, the I/O pins
behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as
input data pins
14
Ground
GND
. Ground for the device
28
Power Supply
Vcc
. Power supply for the device
Notes:
2.
Typical specifications are the mean values measured over a large sample size across normal production process variations and are taken at nominal conditions
(T
A
= 25
°
C, V
CC
). Parameters are guaranteed by design and characterization, and not 100% tested.
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