- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379050 > CY62256LL-55SNI (CYPRESS SEMICONDUCTOR CORP) 256K (32K x 8) Static RAM PDF資料下載
參數(shù)資料
| 型號(hào)： | CY62256LL-55SNI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 256K (32K x 8) Static RAM |
| 中文描述： | 32K X 8 STANDARD SRAM, 55 ns, PDSO28 |
| 封裝： | 0.300 INCH, SOIC-28 |
| 文件頁(yè)數(shù)： | 1/12頁(yè) |
| 文件大?。?/td> | 394K |
| 代理商： | CY62256LL-55SNI |
256K (32K x 8) Static RAM
CY62256
Cypress Semiconductor Corporation
Document #: 38-05248 Rev. *C
3901 North First Street
San Jose
CA 95134
408-943-2600
Revised June 25, 2004
Features
Temperature Ranges
—Commercial: 0°C to 70°C
—Industrial: –40°C to 85°C
—Automotive: –40°C to 125°C
High speed: 55 ns and 70 ns
Voltage range: 4.5V–5.5V operation
Low active power (70 ns, LL version, Com’l and Ind’l)
—275 mW (max.)
Low standby power (70 ns, LL version, Com’l and Ind’l)
—
28
μ
W (max.)
Easy memory expansion with CE and OE features
TTL-compatible inputs and outputs
Automatic power-down when deselected
CMOS for optimum speed/power
Package available in a standard 450-mil-wide (300-mil
body width) 28-lead narrow SOIC, 28-lead TSOP-1,
28-lead reverse TSOP-1, and 600-mil 28-lead PDIP
packages
Functional Description
[1]
The CY62256 is a high-performance CMOS static RAM
organized as 32K words by 8 bits. Easy memory expansion is
provided by an active LOW chip enable (CE) and active LOW
output enable (OE) and three-state drivers. This device has an
automatic
power-down
feature,
consumption by 99.9% when deselected.
An active LOW write enable signal (WE) controls the
writing/reading operation of the memory. When CE and WE
inputs are both LOW, data on the eight data input/output pins
(I/O
0
through I/O
7
) is written into the memory location
addressed by the address present on the address pins (A
0
through A
14
). Reading the device is accomplished by selecting
the device and enabling the outputs, CE and OE active LOW,
while WE remains inactive or HIGH. Under these conditions,
the contents of the location addressed by the information on
address pins are present on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH.
reducing
the
power
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
COLUMN
DECODER
R
S
INPUTBUFFER
POWER
DOWN
WE
OE
I/O
0
CE
I/O
1
I/O
2
I/O
3
512 x 512
ARRAY
I/O
7
I/O
6
I/O
5
I/O
4
A
10
A
1
A
1
A
1
A
0
A
1
A
1
Logic Block Diagram
Note:
1.
For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY62256LL-55ZE | 256K (32K x 8) Static RAM |
| CY62256LL-55ZI | Male insert; Series:Han D; No. of Contacts:64; Gender:Male; Body Material:Polycarbonate; Connecting Termination:Crimp; For Use With:Han 64D; Connector Type:Panel Mount Housing RoHS Compliant: Yes |
| CY62256LL-55ZRE | 256K (32K x 8) Static RAM |
| CY62256LL-55ZC | 256K (32K x 8) Static RAM |
| CY62256LL-55ZRC | 256K (32K x 8) Static RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY62256LL-55SNIT | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
| CY62256LL-55SNXI | 功能描述:IC SRAM 256KBIT 55NS 28SOIC RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:MoBL® 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:移動(dòng) SDRAM 存儲(chǔ)容量:256M（8Mx32） 速度:133MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.95 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:帶卷 (TR) 其它名稱:557-1327-2 |
| CY62256LL-55SNXIT | 功能描述:IC SRAM 256KBIT 55NS 28SOIC RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:MoBL® 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:移動(dòng) SDRAM 存儲(chǔ)容量:256M（8Mx32） 速度:133MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.95 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:帶卷 (TR) 其它名稱:557-1327-2 |
| CY62256LL-55ZI | 制造商:Rochester Electronics LLC 功能描述:256K (32K X 8)- SLOW ASYNCH SRAM - Bulk |
| CY62256LL-55ZXE | 制造商:Rochester Electronics LLC 功能描述:SLOW 3.0V ULTRA LOW POWER 32K X 8 SRAM - Bulk |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。