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參數(shù)資料
| 型號(hào)： | CY62256LL-70SNC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 256K (32K x 8) Static RAM |
| 中文描述： | 32K X 8 STANDARD SRAM, 70 ns, PDSO28 |
| 封裝： | 0.300 INCH, SOIC-28 |
| 文件頁(yè)數(shù)： | 5/12頁(yè) |
| 文件大?。?/td> | 394K |
| 代理商： | CY62256LL-70SNC |
CY62256
Document #: 38-05248 Rev. *C
Page 5 of 12
Switching Characteristics
Over the Operating Range
[7]
Parameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
Write Cycle
[10, 11]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Description
CY62256
55
Min.
CY62256
70
Min.
Unit
Max.
Max.
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z
[8]
OE HIGH to High-Z
[8, 9]
CE LOW to Low-Z
[8]
CE HIGH to High-Z
[8, 9]
CE LOW to Power-up
CE HIGH to Power-down
55
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
55
70
5
5
55
25
70
35
5
5
20
25
5
5
20
25
0
0
55
70
Write Cycle Time
CE LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE LOW to High-Z
[8, 9]
WE HIGH to Low-Z
[8]
55
45
45
0
0
40
25
0
70
60
60
0
0
50
30
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
25
5
5
Switching Waveforms
Notes:
7.
Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
/I
and 100-pF load capacitance.
At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
t
, t
, and t
are specified with C
= 5 pF as in (b) of AC Test Loads. Transition is measured
±
500 mV from steady-state voltage.
10. The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a Write and either signal can terminate
a Write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the Write.
11.
The minimum Write cycle time for Write cycle #3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
12. Device is continuously selected. OE, CE = V
IL
.
13. WE is HIGH for Read cycle.
8.
9.
ADDRESS
DATA OUT
PREVIOUS DATA VALID
DATA VALID
t
RC
t
AA
t
OHA
Read Cycle No. 1
[12, 13]
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY62256LL-70SNC.DS | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 5V 256K-Bit 32K x 8 70ns 28-Pin SNC N |
| CY62256LL-70SNCT | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 5V 256K-Bit 32K x 8 70ns 28-Pin SNC N T/R |
| CY62256LL-70SNCX | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 5V 256K-Bit 32K x 8 70ns 28-Pin SNC N |
| CY62256LL-70SNI | 制造商:Rochester Electronics LLC 功能描述:256K (32K X 8)- SLOW ASYNCH SRAM - Bulk |
| CY62256LL-70SNIT | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
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